LSM320DLTR STMicroelectronics, LSM320DLTR Datasheet - Page 41

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LSM320DLTR

Manufacturer Part Number
LSM320DLTR
Description
IC LINEAR
Manufacturer
STMicroelectronics
Datasheet

Specifications of LSM320DLTR

Lead Free Status / Rohs Status
Compliant
LSM320DL
7.26
Table 67.
Table 68.
Table 69.
CTRL_REG3_G (22h)
Table 70.
Table 71.
HPM1-
HPM0
HPCF3-
HPCF0
I1_Int1
I1_Boot
H_Lactive
I1_Int1
HPCF-0
0000
0001
0010
0011
0100
0101
0110
0111
1000
1001
HPM1
0
0
1
1
CTRL_REG2_G description
High pass filter mode configuration
High pass filter cut-off frequency configuration [Hz]
CTRL_REG1_G register
CTRL_REG3_G description
I1_Boot
High pass filter mode selection. Default value: 00
Refer to
High pass filter cut-off frequency selection
Refer to
Interrupt enable on INT1 pin. Default value 0. (0: disable; 1: enable)
Boot status available on INT1. Default value 0. (0: disable; 1: enable)
Interrupt active configuration on INT1. Default value 0. (0: high; 1:low)
ODR = 100 Hz
Table 68
Table 69
H_Lactive
0.05
0.02
0.01
0.5
0.2
0.1
8
4
2
1
Doc ID 018845 Rev 1
HPM0
0
1
0
1
PP_OD
ODR = 200 Hz
0.05
0.02
0.5
0.2
0.1
15
8
4
2
1
Normal mode (reset reading HP_RESET_FILTER
Reference signal for filtering
Normal mode
Autoreset an interrupt event
I2_DRDY
ODR = 400 Hz
High pass filter mode
I2_WTM
0.05
0.2
0.5
0.1
30
15
8
4
2
1
Registers description
I2_ORun
ODR = 800 Hz
0.5
0.2
0.1
56
30
15
I2_Empty
8
4
2
1
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