LSM320DLTR STMicroelectronics, LSM320DLTR Datasheet - Page 27

• Manufacturer Part Number: LSM320DLTR
• Description: IC LINEAR
• Manufacturer: STMicroelectronics

Specifications of LSM320DLTR

• Lead Free Status / Rohs Status: Compliant

LSM320DL
5.2.3
bit 0: WRITE bit. The value is 0.
bit 1: MS bit. When 0, do not increment address, when 1, increment address in multiple
writing.
bit 2 -7: address AD(5:0). This is the address field of the indexed register.
bit 8-15: data DI(7:0) (write mode). This is the data that is written inside the device (MSb
first).
bit 16-... : data DI(...-8). Further data in multiple byte writing.
Figure 10. Multiple bytes SPI write protocol (2 bytes example)
SPI read in 3-wire mode
3-wire mode is entered by setting to ‘1’ bit SIM (SPI serial interface mode selection) in
CTRL_REG4.
Figure 11. SPI read protocol in 3-wire mode
The SPI read command is performed with 16 clock pulses:
bit 0: READ bit. The value is 1.
bit 1: MS bit. When 0, do not increment address, when 1, increment address in multiple
reading.
bit 2-7: address AD(5:0). This is the address field of the indexed register.
bit 8-15: data DO(7:0) (read mode). This is the data that is read from the device (MSb first).
Multiple read command is also available in 3-wire mode.
SPC
SDI
CS
SDI/O
SPC
CS
RW
MS
AD5 AD4 AD3 AD2 AD1 AD0
RW
MS
AD5 AD4 AD3 AD2 AD1 AD0
Doc ID 018845 Rev 1
DI7 DI6 DI5 DI4 DI3 DI2 DI1 DI0 DI15 DI14 DI13 DI12 DI11 DI10 DI9 DI8
DO7 DO6 DO5 DO4 DO3 DO2 DO1 DO0
Digital interfaces
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