LSM320DLTR STMicroelectronics, LSM320DLTR Datasheet - Page 32

• Manufacturer Part Number: LSM320DLTR
• Description: IC LINEAR
• Manufacturer: STMicroelectronics

Specifications of LSM320DLTR

• Lead Free Status / Rohs Status: Compliant

Registers description
7.4
7.5
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Table 26.
CTRL_REG4_A (23h)
Table 27.
1. This bit must be set to ‘0’ for correct operation.
Table 28.
CTRL_REG5_A (24h)
Table 29.
1. This bit must be set to ‘0’ for correct operation.
Table 30.
I1_DRDY1
I1_DRDY2
I1_WTM
I1_OVERRUN
BLE
FS1-FS0
HR
SIM
BOOT
FIFO_EN
LIR_INT1
D4D_INT1
BOOT
0
(1)
FIFO_EN
CTRL_REG3_A description (continued)
CTRL_REG4_A register
CTRL_REG4_A description
CTRL_REG5_A register
CTRL_REG5_A description
BLE
Big/little endian data selection. Default value 0.
(0: data LSB @ lower address; 1: data MSB @ lower address)
Full scale selection. default value: 00
(00: +/- 2G; 01: +/- 4G; 10: +/- 8G; 11: +/- 16G)
High resolution output mode: default value: 0
(0: high resolution disable; 1: high resolution enable)
SPI serial interface mode selection. Default value: 0
(0: 4-wire interface; 1: 3-wire interface).
Reboot memory content. Default value: 0
(0: normal mode; 1: reboot memory content)
FIFO enable. Default value: 0
(0: FIFO disable; 1: FIFO enable)
Latch interrupt request on INT1_SRC register, with INT1_SRC register
cleared by reading INT1_SRC itself. Default value: 0.
(0: interrupt request not latched; 1: interrupt request latched)
4D enable: 4D detection is enabled on INT1 when 6D bit on INT1_CFG is set
to 1.
DRDY1 interrupt on INT1. Default value 0.
(0: disable; 1: enable)
DRDY2 interrupt on INT1. Default value 0.
(0: disable; 1: enable)
FIFO Watermark interrupt on INT1. Default value 0.
(0: disable; 1: enable)
FIFO Overrun interrupt on INT1. Default value 0.
(0: disable; 1: enable)
--
FS1
Doc ID 018845 Rev 1
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LIR_INT1
FS0
D4D_INT1
HR
0
(1)
0
(1)
0
(1)
0
LSM320DL
(1)
SIM