LSM320DLTR STMicroelectronics, LSM320DLTR Datasheet
LSM320DLTR
Specifications of LSM320DLTR
Related parts for LSM320DLTR
LSM320DLTR Summary of contents
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... LGA package. Table 1. Device summary Temperature Order codes range [°C] LSM320DL -40 to +85 LSM320DLTR Doc ID 018845 Rev 1 LSM320DL Preliminary data Package Packing Tray LGA 28L Tape and reel 1/53 www ...
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Contents Contents 1 Block diagram and pin description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9 1.1 Block ...
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LSM320DL 7 Registers description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ...
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Contents 7.33 OUT_Z_L_G (2Ch), OUT_Z_H_G (2Dh 7.34 FIFO_CTRL_REG_G (2Eh ...
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LSM320DL List of tables Table 1. Device summary . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ...
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List of tables Table 49. INT1_DURATION_A description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ...
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LSM320DL Table 100. INT1_THS_ZL_G description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ...
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List of figures List of figures Figure 1. Block diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ...
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LSM320DL 1 Block diagram and pin description 1.1 Block diagram Figure 1. Block diagram Sensing Block ( (Ω Feedback+ Feedback- Drive- Drive+ REFERENCE CONTROL LOGIC & INTERRUPT GEN. ...
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Block diagram and pin description 1.2 Pin description Figure 2. Pin connection DIRECTION OF DETECTABLE ACCELERATIONS X + Ω DIRECTION OF +Ω DETECTABLE X ANGULAR RATE X Table 2. Pin description Pin# 1 SDA/SDI_A ...
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LSM320DL Table 2. Pin description (continued) Pin Name Gyroscope: SPI enable CS_G 2 I C/SPI mode selection (1: SPI idle mode ...
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Module specifications 2 Module specifications 2.1 Mechanical characteristics @ Vdd = 3V °C unless otherwise noted Table 3. Mechanical characteristics Symbol Parameter Linear acceleration LA_FS measurement range Angular rate G_FS measurement range Linear acceleration LA_So sensitivity G_So ...
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LSM320DL 1. Typical specifications are not guaranteed. 2. Verified by wafer level test and measurement of initial offset and sensitivity. 3. Typical Zero-g level offset value after MSL3 preconditioning. 4. Offset can be eliminated by enabling the built-in high pass ...
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Module specifications 2.3 Temperature sensor characteristics @ Vdd =3 °C, unless otherwise noted. Table 5. Temperature sensor characteristics Symbol Parameter Temperature sensor TSDr output change vs. temperature Temperature refresh TODR rate Operating Top temperature range 1. Typical ...
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LSM320DL 2.4 Communication interface characteristics 2.4.1 SPI - serial peripheral interface Subject to general operating conditions for Vdd and Top. Table 6. SPI slave timing values Symbol tc(SPC) SPI clock cycle fc(SPC) SPI clock frequency tsu(CS) CS setup time th(CS) ...
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Module specifications 2 2.4 inter IC control interface Subject to general operating conditions for Vdd and Top. 2 Table slave timing values Symbol Parameter f SCL clock frequency (SCL) t SCL clock low time ...
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LSM320DL 2.5 Absolute maximum ratings Stresses above those listed as “absolute maximum ratings” may cause permanent damage to the device. This is a stress rating only and functional operation of the device under these conditions is not implied. Exposure to ...
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Module specifications 2.6 Terminology 2.6.1 Sensitivity Linear acceleration sensitivity can be determined, for example, by applying 1 g acceleration to the device. As the sensor can measure DC accelerations this can be done easily by pointing the axis of interest ...
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LSM320DL 3 Functionality The LSM320DL is a system-in-package featuring a 3D digital accelerometer and a 2D digital gyroscope. The complete device includes specific sensing elements and two IC interfaces able to measure both the acceleration and angular rate applied to ...
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Application hints 4 Application hints Figure 5. LSM320DL electrical connection Vdd_IO C5 GND 10 11 Res Vdd_IO_G SCL_G 14 Res 15 Vdd Table 9. Part list 4.1 External capacitors The device core is supplied through Vdd line. Power supply decoupling ...
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LSM320DL The functions, the threshold, and the timing of the two interrupt pins for each sensor can be completely programmed by the user though the SPI/I 4.2 Soldering information The LGA package is compliant with the ECOPACK It is qualified ...
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Digital interfaces 5 Digital interfaces The registers embedded inside the LSM320DL may be accessed through both the I SPI serial interfaces. The latter may be SW configured to operate either in 3-wire or 4-wire interface mode. To select/exploit the I ...
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LSM320DL 2 5.1 operation The transaction on the bus is started through a START (ST) signal. A START condition is defined as a HIGH to LOW transition on the data line while the SCL line is held HIGH. ...
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Digital interfaces state. Data transfer only continues when the receiver is ready for another byte and releases the data line slave receiver doesn’t acknowledge the slave address (i. not able to receive because it is performing ...
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LSM320DL 5.2 SPI bus interface The LSM320DL SPI is a bus slave. The SPI allows to write and read the registers of the device. The serial interface interacts with the outside world with 4 wires: CS, SPC, SDI, and SDO.(SPC, ...
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Digital interfaces 5.2.1 SPI read Figure 7. SPI read protocol CS SPC SDI SDO The SPI Read command is performed with 16 clock pulses. Multiple byte read command is performed adding blocks of 8 clock pulses at the previous one. ...
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LSM320DL bit 0: WRITE bit. The value is 0. bit 1: MS bit. When 0, do not increment address, when 1, increment address in multiple writing. bit 2 -7: address AD(5:0). This is the address field of the indexed register. ...
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Register mapping 6 Register mapping Table 18 below provides a listing of the 8-bit registers embedded in the device and the related addresses: Table 18. Register address map Name Address Reserved (do not modify) 001100xb CTRL_REG1_A 001100xb CTRL_REG2_A 001100xb CTRL_REG3_A ...
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LSM320DL Table 18. Register address map (continued) Name Address TIME_LATENCY_A 001100xb TIME_WINDOW_A 001100xb Reserved (do not modify) 001100xb Reserved 110100xb CTRL_REG1_G 110100xb CTRL_REG2_G 110100xb CTRL_REG3_G 110100xb CTRL_REG4_G 110100xb CTRL_REG5_G 110100xb REFERENCE_G 110100xb OUT_TEMP_G 110100xb STATUS_REG_G 110100xb OUT_X_L_G 110100xb OUT_X_H_G 110100xb ...
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Registers description 7 Registers description The device contains a set of registers which are used to control its behavior and to retrieve acceleration, angular rate and temperature data. The registers address, made of 7 bits, is used to identify them ...
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LSM320DL 7.2 CTRL_REG2_A (21h) Table 22. CTRL_REG2_A register HPM1 HPM0 Table 23. CTRL_REG2_A description HPM1 -HPM0 High pass filter mode selection. Default value: 00 Refer to HPCF2 - High pass filter cut-off frequency selection HPCF1 Filtered data selection. Default value: ...
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Registers description Table 26. CTRL_REG3_A description (continued) I1_DRDY1 I1_DRDY2 I1_WTM I1_OVERRUN 7.4 CTRL_REG4_A (23h) Table 27. CTRL_REG4_A register (1) 0 BLE 1. This bit must be set to ‘0’ for correct operation. Table 28. CTRL_REG4_A description BLE FS1-FS0 HR SIM ...
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LSM320DL 7.6 CTRL_REG6_A (25h) Table 31. CTRL_REG6_A register I2_CLICKen I2_INT1 1. This bit must be set to ‘0’ for correct operation. Table 32. CTRL_REG6 description I2_CLICKen I2_INT1 BOOT_I2 H_LACTIVE 7.7 REFERENCE/DATACAPTURE_A (26h) Table 33. REFERENCE_A register Ref7 Ref6 Table 34. ...
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Registers description Table 36. STATUS_REG_A register description (continued) ZDA Z axis new data available. Default value: 0 (0: a new data for the Z-axis is not yet available new data for the Z-axis is available) YDA Y axis ...
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LSM320DL 7.13 FIFO_SRC_REG_A (2Fh) Table 40. FIFO_SRC_REG_A register WTM OVRN_FIFO 7.14 INT1_CFG_A (30h) Table 41. INT1_CFG_REG_A register AOI 6D ZUPE Table 42. INT1_CFG_REG_A description AOI AND/OR combination of interrupt events. Default value: 0. Refer to 6D 6-direction detection function enabled. ...
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Registers description AOI-6D = ‘01’ is movement recognition. An interrupt is generated when orientation moves from unknown zone to known zone. The interrupt signal stays for a duration ODR. AOI-6D = ‘11’ is direction recognition. An interrupt is generated when ...
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LSM320DL 7.17 INT1_DURATION_A (33h) Table 48. INT1_DURATION_Aregister 0 D6 Table 49. INT1_DURATION_A description bits set the minimum duration of the interrupt 1 event to be recognized. Duration steps and maximum values depend on the ...
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Registers description Table 53. CLICK_SRC_A description IA Interrupt active. Default value: 0 (0: no interrupt has been generated; 1: one or more interrupts have been generated) DCLICK Double CLICK-CLICK enable. Default value: 0 (0: double CLICK-CLICK detection dis- able, 1: ...
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LSM320DL Table 59. TIME_LATENCY_A description TLA7-TLA0 7.23 TIME WINDOW_A (3Dh) Table 60. TIME_WINDOW_A register TW7 TW6 Table 61. TIME_WINDOW_A description TW7-TW0 7.24 CTRL_REG1_G (20h) Table 62. CTRL_REG1_G register DR1 DR0 1. This bit must be set to ‘0’ for correct ...
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Registers description Table 64. DR and BW configuration setting DR <1:0> Combination of PD, Zen, Xen are used to set the device in different ...
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LSM320DL Table 67. CTRL_REG2_G description HPM1- High pass filter mode selection. Default value: 00 HPM0 Refer to HPCF3- High pass filter cut-off frequency selection HPCF0 Refer to Table 68. High pass filter mode configuration HPM1 Table ...
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Registers description Table 71. CTRL_REG3_G description (continued) PP_OD Push-pull/open drain. Default value: 0. (0: push-pull; 1: open drain) I2_DRDY Date ready on DRDY/INT2. Default value 0. (0: disable; 1: enable) I2_WTM FIFO watermark interrupt on DRDY/INT2. Default value: 0. (0: ...
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LSM320DL Table 75. CTRL_REG5_G description (continued) INT1_Sel1- INT1_Sel0 Out_Sel1- Out_Sel0 Figure 12. INT1_Sel and Out_Sel configuration block diagram ADC LPF1 Table 76. Out_Sel configuration setting Hpen Table 77. INT_SEL configuration setting Hpen x x INT1 selection ...
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Registers description Table 77. INT_SEL configuration setting (continued) Hpen 0 1 7.29 REFERENCE/DATACAPTURE_G (25h) Table 78. REFERENCE_G register Ref7 Ref6 Table 79. REFERENCE_G register description Ref 7-Ref0 7.30 OUT_TEMP_G (26h) Table 80. OUT_TEMP_G register Temp7 Temp6 Table 81. OUT_TEMP_G register ...
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LSM320DL Table 83. STATUS_REG_G description (continued) ZXDA X, Z-axis new data available. Default value: 0 (0: a new set of data is not yet available new set of data is available) ZDA Z-axis new data available. Default value: ...
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Registers description Table 88. FIFO_SRC_G register description WTM OVRN EMPTY FSS4-FSS1 7.36 INT1_CFG_G (30h) Table 89. INT1_CFG_G register AND/OR LIR 1. This bit must be set to ‘0’ for correct operation. Table 90. INT1_CFG_G description AND/OR combination of interrupt events. ...
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LSM320DL Table 92. INT1_SRC_G description Interrupt active. Default value (0: no interrupt has been generated; 1: one or more interrupts have been generated high. Default value: 0 (0: no interrupt high event has occurred) ...
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Registers description Table 98. INT1_THS_ZH_G description THSZ14 - THSZ9 7.41 INT1_THS_ZL_G (37h) Table 99. INT1_THS_ZL_G register THSZ7 THSZ6 Table 100. INT1_THS_ZL_G description THSZ7 - THSZ0 7.42 INT1_DURATION_G (38h) Table 101. INT1_DURATION_G register WAIT D6 Table 102. INT1_DURATION_G description WAIT D6 ...
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LSM320DL Figure 13. Wait disabled Figure 14. Wait enabled Doc ID 018845 Rev 1 Registers description 49/53 ...
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Package information 8 Package information In order to meet environmental requirements, ST offers these devices in different grades of ® ECOPACK packages, depending on their level of environmental compliance. ECOPACK specifications, grade definitions, and product status are available at: www.st.com. ...
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LSM320DL Table 103. LGA 28L 7.5 x 4.4 x 1.1 mechanical data Dim Figure 15. LGA 28L 7.5 x 4.4 x 1.1 package drawing ...
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Revision history 9 Revision history Table 104. Document revision history Date 18-May-2011 52/53 Revision 1 Initial release. Doc ID 018845 Rev 1 LSM320DL Changes ...
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... LSM320DL Information in this document is provided solely in connection with ST products. STMicroelectronics NV and its subsidiaries (“ST”) reserve the right to make changes, corrections, modifications or improvements, to this document, and the products and services described herein at any time, without notice. All ST products are sold pursuant to ST’s terms and conditions of sale. ...