LSM320DLTR STMicroelectronics, LSM320DLTR Datasheet - Page 23

• Manufacturer Part Number: LSM320DLTR
• Description: IC LINEAR
• Manufacturer: STMicroelectronics

Specifications of LSM320DLTR

• Lead Free Status / Rohs Status: Compliant

LSM320DL
5.1.1
Table 15.
Master
Slave
ST SAD+W
I
The transaction on the bus is started through a START (ST) signal. A START condition is
defined as a HIGH to LOW transition on the data line while the SCL line is held HIGH. After
this has been transmitted by the master, the bus is considered busy. The next byte of data
transmitted after the start condition contains the address of the slave in the first 7 bits and
the eighth bit tells whether the master is receiving data from the slave or transmitting data to
the slave. When an address is sent, each device in the system compares the first seven bits
after a start condition with its address. If they match, the device considers itself addressed
by the master.
Data transfer with acknowledge is mandatory. The transmitter must release the SDA line
during the acknowledge pulse. The receiver must then pull the data line LOW so that it
remains stable low during the HIGH period of the acknowledge clock pulse. A receiver which
has been addressed is obliged to generate an acknowledge after each byte of data
received.
The I
protocol must be adhered to. After the start condition (ST), a slave address is sent, once a
slave acknowledge (SAK) has been returned, an 8-bit sub-address (SUB) is transmitted: the
7 LSb represent the actual register address while the MSB enables address auto increment.
If the MSb of the SUB field is ‘1’, the SUB (register address) is automatically increased to
allow multiple data read/write.
Table 12.
Table 13.
Table 14.
Transfer when master is receiving (reading) multiple bytes of data from slave
Data are transmitted in byte format (DATA). Each data transfer contains 8 bits. The number
of bytes transferred per transfer is unlimited. Data is transferred with the most significant bit
(MSb) first. If a receiver can’t receive another complete byte of data until it has performed
some other function, it can hold the clock line, SCL LOW, to force the transmitter into a wait
2
Master
Master
Slave
C operation
Slave
Master
Slave
2
C embedded inside the LSM320DL behaves as a slave device and the following
ST
SAK
ST
Transfer when master is writing one byte to slave
Transfer when master is writing multiple bytes to slave:
Transfer when master is receiving (reading) one byte of data from slave:
ST
SAD + W
SUB
SAD + W
SAK
SAD + W
SAK
SR SAD+R
SAK
Doc ID 018845 Rev 1
SUB
SAK
SUB
SAK
SAK
SAK
SUB
SR
DATA
SAD + R
DATA
MAK
SAK
DATA
SAK
SAK
DATA
MAK
DATA
DATA
DATA
Digital interfaces
SAK
NMAK
SAK
NMAK
SP
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SP
SP
SP