LSM320DLTR STMicroelectronics, LSM320DLTR Datasheet - Page 24

• Manufacturer Part Number: LSM320DLTR
• Description: IC LINEAR
• Manufacturer: STMicroelectronics

Specifications of LSM320DLTR

• Lead Free Status / Rohs Status: Compliant

Digital interfaces
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state. Data transfer only continues when the receiver is ready for another byte and releases
the data line. If a slave receiver doesn’t acknowledge the slave address (i.e. it is not able to
receive because it is performing some real time function), the data line must be left HIGH by
the slave. The master can then abort the transfer. A LOW to HIGH transition on the SDA line
while the SCL line is HIGH is defined as a STOP condition. Each data transfer must be
terminated by the generation of a STOP (SP) condition.
In order to read multiple bytes, it is necessary to assert the most significant bit of the sub-
address field. In other words, SUB(7) must be equal to 1 while SUB(6-0) represents the
address of the first register to be read.
In the presented communication format, MAK is Master Acknowledge, and NMAK is No
Master Acknowledge.
Default address:
The SDO/SA0 pad can be used to modify less significant bits of the device address. If the
SA0 pad is connected to voltage supply, LSb is ‘1’ (ex. address 0011001b), or else, if the
SA0 pad is connected to ground, the LSb value is ‘0’ (ex address 0011000b).
The slave address is completed with a Read/Write bit. If the bit is ‘1’ (Read), a repeated
START (SR) condition must be issued after the two sub-address bytes; if the bit is ‘0’ (Write)
the master transmits to the slave with direction unchanged.
how the SAD+Read/Write bit pattern is composed, listing all the possible configurations.
Linear acceleration address: the default (factory) 7-bit slave address is
001100xb.
Table 16.
Angular rate sensor: the default (factory) 7-bit slave address is 110100xb.
Table 17.
Command
Command
Read
Write
Read
Write
Read
Write
Read
Write
Linear acceleration SAD+Read/Write patterns
Angular rate SAD+Read/Write patterns
SAD[6:1]
SAD[6:1]
001100
001100
001100
001100
110100
110100
110100
110100
Doc ID 018845 Rev 1
SAD[0] = SA0
SAD[0] = SA0
0
0
1
1
0
0
1
1
Table 16
R/W
R/W
1
0
1
0
1
0
1
0
and
00110001 (31h)
00110000 (30h)
00110011 (33h)
00110010 (32h)
11010001 (F1h)
11010000 (F0h)
11010011 (F3h)
11010010 (F2h)
Table 17
SAD+R/W
SAD+R/W
LSM320DL
explain