LSM320DLTR STMicroelectronics, LSM320DLTR Datasheet - Page 36

• Manufacturer Part Number: LSM320DLTR
• Description: IC LINEAR
• Manufacturer: STMicroelectronics

Specifications of LSM320DLTR

• Lead Free Status / Rohs Status: Compliant

Registers description
7.15
7.16
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AOI-6D = ‘01’ is movement recognition. An interrupt is generated when orientation moves
from unknown zone to known zone. The interrupt signal stays for a duration ODR.
AOI-6D = ‘11’ is direction recognition. An interrupt is generated when orientation is inside a
known zone. The interrupt signal stays until orientation is inside the zone.
INT1_SRC_A (31h)
Table 44.
Table 45.
Interrupt 1 source register. Read only register.
Reading at this address clears the INT1_SRC IA bit (and the interrupt signal on the INT 1
pin) and allows the refreshment of data in the INT1_SRC register if the latched option is
chosen.
INT1_THS_A (32h)
Table 46.
Table 47.
THS6 - THS0
YH
XH
ZH
ZL
YL
XL
IA
0
0
Interrupt active. Default value: 0
(0: no interrupt has been generated; 1: one or more interrupts have been generated)
Z high. Default value: 0
(0: no interrupt, 1: Z high event has occurred)
Z low. Default value: 0
(0: no interrupt; 1: Z low event has occurred)
Y high. Default value: 0
(0: no interrupt, 1: Y high event has occurred)
Y low. Default value: 0
(0: no interrupt, 1: Y low event has occurred)
X high. Default value: 0
(0: no interrupt, 1: X high event has occurred)
X low. Default value: 0
(0: no interrupt, 1: X low event has occurred)
INT1_SRC_A register
INT1_SRC_A description
INT1_THS_A register
INT1_THS_A description
THS6
IA
Interrupt 1 threshold. Default value: 000 0000
THS5
ZH
Doc ID 018845 Rev 1
THS4
ZL
THS3
YH
THS2
YL
THS1
XH
LSM320DL
THS0
XL