PIC18F26K80-E/SP Microchip Technology Inc., PIC18F26K80-E/SP Datasheet - Page 86

• Manufacturer Part Number: PIC18F26K80-E/SP
• Description: 28 SPDIP .300IN TUBE, ECAN, 64KB FLASH, 4KB RAM, 16 MIPS, 12-BIT ADC, CTMU
• Manufacturer: Microchip Technology Inc.

Specifications of PIC18F26K80-E/SP

• A/d Inputs: 8-Channel, 12-Bit
• Comparators: 2
• Cpu Speed: 16 MIPS
• Eeprom Memory: 256 Bytes
• Input Output: 24
• Interface: I2C/SPI/UART/USART
• Memory Type: Flash
• Number Of Bits: 8
• Package Type: 28-pin SPDIP
• Programmable Memory: 64K Bytes
• Ram Size: 3.6K Bytes
• Speed: 64 MHz
• Temperature Range: –40 to 125 °C
• Timers: 2-8-bit, 3-16-bit
• Voltage, Range: 1.8-5.5 V
• Lead Free Status / Rohs Status: RoHS Compliant part

PIC18F66K80 FAMILY
5.6.2
The Oscillator Start-up Timer (OST) provides a
1024 oscillator cycle (from OSC1 input) delay after the
PWRT delay is over (Parameter 33). This ensures that
the crystal oscillator or resonator has started and
stabilized.
The OST time-out is invoked only for XT, LP, HS and
HSPLL modes and only on Power-on Reset or on exit
from most power-managed modes.
5.6.3
With the PLL enabled in its PLL mode, the time-out
sequence following a Power-on Reset is slightly differ-
ent from other oscillator modes. A separate timer is
used to provide a fixed time-out that is sufficient for the
PLL to lock to the main oscillator frequency. This PLL
lock time-out (T
oscillator start-up time-out.
TABLE 5-2:
FIGURE 5-3:
DS39977C-page 86
HSPLL
HS, XT, LP
EC, ECIO
RC, RCIO
INTIO1, INTIO2
Note 1:
INTERNAL RESET
PWRT TIME-OUT
Configuration
INTERNAL POR
OST TIME-OUT
2:
Oscillator
66 ms (65.5 ms) is the nominal Power-up Timer (PWRT) delay.
2 ms is the nominal time required for the PLL to lock.
OSCILLATOR START-UP TIMER
(OST)
PLL LOCK TIME-OUT
MCLR
PLL
V
TIME-OUT IN VARIOUS SITUATIONS
DD
) is typically 2 ms and follows the
TIME-OUT SEQUENCE ON POWER-UP (MCLR TIED TO V
66 ms
66 ms
(1)
PWRTEN = 0
+ 1024 T
(1)
66 ms
66 ms
66 ms
+ 1024 T
OSC
(1)
(1)
(1)
Power-up and Brown-out
+ 2 ms
OSC
Preliminary
T
PWRT
(2)
5.6.4
On power-up, the time-out sequence is as follows:
1.
2.
The total time-out will vary based on oscillator configu-
ration and the status of the PWRT.
Figure
depict time-out sequences on power-up, with the
Power-up Timer enabled and the device operating in
HS Oscillator mode. Figures
to devices operating in XT or LP modes. For devices in
RC mode and with the PWRT disabled, on the other
hand, there will be no time-out at all.
Since the time-outs occur from the POR pulse, if MCLR
is kept low long enough, all time-outs will expire. Bring-
ing MCLR high will begin execution immediately
(Figure
synchronize more than one PIC18FXXXX device
operating in parallel.
1024 T
T
PWRTEN = 1
After the POR pulse has cleared, PWRT
time-out is invoked (if enabled).
Then, the OST is activated.
OST
1024 T
5-4,
OSC
5-5). This is useful for testing purposes or to
—
—
—
TIME-OUT SEQUENCE
Figure
+ 2 ms
OSC
(2)
5-5,
 2011 Microchip Technology Inc.
Figure 5-6
DD
5-3
Power-Managed Mode
, V
1024 T
DD
through
RISE < T
1024 T
and
Exit from
OSC
—
—
—
Figure 5-7
5-6
+ 2 ms
OSC
Figure
also apply
PWRT
(2)
5-3,
)
all