PIC18F26K80-E/SP Microchip Technology Inc., PIC18F26K80-E/SP Datasheet - Page 70

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PIC18F26K80-E/SP

Manufacturer Part Number
PIC18F26K80-E/SP
Description
28 SPDIP .300IN TUBE, ECAN, 64KB FLASH, 4KB RAM, 16 MIPS, 12-BIT ADC, CTMU
Manufacturer
Microchip Technology Inc.
Datasheet

Specifications of PIC18F26K80-E/SP

A/d Inputs
8-Channel, 12-Bit
Comparators
2
Cpu Speed
16 MIPS
Eeprom Memory
256 Bytes
Input Output
24
Interface
I2C/SPI/UART/USART
Memory Type
Flash
Number Of Bits
8
Package Type
28-pin SPDIP
Programmable Memory
64K Bytes
Ram Size
3.6K Bytes
Speed
64 MHz
Temperature Range
–40 to 125 °C
Timers
2-8-bit, 3-16-bit
Voltage, Range
1.8-5.5 V
Lead Free Status / Rohs Status
RoHS Compliant part

Available stocks

Company
Part Number
Manufacturer
Quantity
Price
Part Number:
PIC18F26K80-E/SP
Manufacturer:
SILICON
Quantity:
210
PIC18F66K80 FAMILY
If the IRCF bits and the INTSRC bit are all clear, the
INTOSC output (HF-INTOSC/MF-INTOSC) is not
enabled and the HFIOFS and MFIOFS bits will remain
clear. There will be no indication of the current clock
source. The LF-INTOSC source is providing the device
clocks.
TABLE 4-3:
Clocks to the device continue while the INTOSC source
stabilizes after an interval of T
Table
If the IRCF bits were previously at a non-zero value, or
if INTSRC was set before setting SCS1 and the
INTOSC source was already stable, the HFIOFS or
MFIOFS bit will remain set.
DS39977C-page 70
IRCF<2:0>
Non-Zero
Non-Zero
31-11).
000
000
000
INTERNAL OSCILLATOR FREQUENCY STABILITY BITS
INTSRC
0
1
1
x
x
IOBST
(Parameter 39,
MFIOSEL
x
0
1
0
1
Preliminary
MFIOFS = 0, HFIOFS = 0 and clock source is LF-INTOSC
MFIOFS = 0, HFIOFS = 1 and clock source is HF-INTOSC
MFIOFS = 1, HFIOFS = 0 and clock source is MF-INTOSC
MFIOFS = 0, HFIOFS = 1 and clock source is HF-INTOSC
MFIOFS = 1, HFIOFS = 0 and clock source is MF-INTOSC
Status of MFIOFS or HFIOFS when INTOSC is Stable
If the IRCF bits are changed from all clear (thus,
enabling the INTOSC output) or if INTSRC or
MFIOSEL is set, the HFIOFS or MFIOFS bit is set after
the INTOSC output becomes stable. For details, see
Table
On transitions from RC_RUN mode to PRI_RUN mode,
the device continues to be clocked from the INTOSC
multiplexer while the primary clock is started. When the
primary clock becomes ready, a clock switch to the
primary clock occurs (see
switch is complete, the HFIOFS or MFIOFS bit is
cleared, the OSTS bit is set and the primary clock is
providing the device clock. The IDLEN and SCS bits
are not affected by the switch. The LF-INTOSC source
will continue to run if either the WDT or the Fail-Safe
Clock Monitor (FSCM) is enabled.
4-3.
 2011 Microchip Technology Inc.
Figure
4-4). When the clock

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