PIC18F26K80-E/SP Microchip Technology Inc., PIC18F26K80-E/SP Datasheet - Page 394

• Manufacturer Part Number: PIC18F26K80-E/SP
• Description: 28 SPDIP .300IN TUBE, ECAN, 64KB FLASH, 4KB RAM, 16 MIPS, 12-BIT ADC, CTMU
• Manufacturer: Microchip Technology Inc.

Specifications of PIC18F26K80-E/SP

• A/d Inputs: 8-Channel, 12-Bit
• Comparators: 2
• Cpu Speed: 16 MIPS
• Eeprom Memory: 256 Bytes
• Input Output: 24
• Interface: I2C/SPI/UART/USART
• Memory Type: Flash
• Number Of Bits: 8
• Package Type: 28-pin SPDIP
• Programmable Memory: 64K Bytes
• Ram Size: 3.6K Bytes
• Speed: 64 MHz
• Temperature Range: –40 to 125 °C
• Timers: 2-8-bit, 3-16-bit
• Voltage, Range: 1.8-5.5 V
• Lead Free Status / Rohs Status: RoHS Compliant part

PIC18F66K80 FAMILY
26.6
When enabled, the HLVD circuitry continues to operate
during Sleep. If the device voltage crosses the trip
point, the HLVDIF bit will be set and the device will
wake-up from Sleep. Device execution will continue
from the interrupt vector address if interrupts have
been globally enabled.
TABLE 26-1:
DS39977C-page 394
HLVDCON
INTCON
PIR2
PIE2
IPR2
TRISA
Legend: — = unimplemented, read as ‘ 0 ’. Shaded cells are not used by the HLVD module.
Note 1:
Name
Operation During Sleep
PORTA<7:6> and their direction bits are individually configured as port pins based on various primary
oscillator modes. When disabled, these bits read as ‘ 0 ’.
VDIRMAG
GIE/GIEH
TRISA7
OSCFIE
OSCFIP
OSCFIF
REGISTERS ASSOCIATED WITH HIGH/LOW-VOLTAGE DETECT MODULE
Bit 7
(1)
PEIE/GIEL
TRISA6
BGVST
Bit 6
—
—
—
(1)
TMR0IE
TRISA5
IRVST
Bit 5
—
—
—
Preliminary
HLVDEN
INT0IE
Bit 4
—
—
—
—
26.7
A device Reset forces all registers to their Reset state.
This forces the HLVD module to be turned off.
HLVDL3
TRISA3
BCLIF
BCLIE
BCLIP
RBIE
Bit 3
Effects of a Reset
HLVDL2
TMR0IF
HLVDIF
HLVDIE
HLVDIP
TRISA2
Bit 2
 2011 Microchip Technology Inc.
HLVDL1
TMR3IE
TMR3IP
TMR3IF
TRISA1
INT0IF
Bit 1
TMR3GIE
TMR3GIP
TMR3GIF
HLVDL0
TRISA0
RBIF
Bit 0