PIC18F26K80-E/SP Microchip Technology Inc., PIC18F26K80-E/SP Datasheet - Page 83

• Manufacturer Part Number: PIC18F26K80-E/SP
• Description: 28 SPDIP .300IN TUBE, ECAN, 64KB FLASH, 4KB RAM, 16 MIPS, 12-BIT ADC, CTMU
• Manufacturer: Microchip Technology Inc.

Specifications of PIC18F26K80-E/SP

• A/d Inputs: 8-Channel, 12-Bit
• Comparators: 2
• Cpu Speed: 16 MIPS
• Eeprom Memory: 256 Bytes
• Input Output: 24
• Interface: I2C/SPI/UART/USART
• Memory Type: Flash
• Number Of Bits: 8
• Package Type: 28-pin SPDIP
• Programmable Memory: 64K Bytes
• Ram Size: 3.6K Bytes
• Speed: 64 MHz
• Temperature Range: –40 to 125 °C
• Timers: 2-8-bit, 3-16-bit
• Voltage, Range: 1.8-5.5 V
• Lead Free Status / Rohs Status: RoHS Compliant part

5.2
The MCLR pin provides a method for triggering an
external Reset of the device. A Reset is generated by
holding the pin low. These devices have a noise filter in
the MCLR Reset path which detects and ignores small
pulses.
The MCLR pin is not driven low by any internal Resets,
including the WDT.
In PIC18F66K80 family devices, the MCLR input can
be disabled with the MCLRE Configuration bit. When
MCLR is disabled, the pin becomes a digital input. See
Section 11.6 “PORTE, TRISE and LATE Registers”
for more information.
5.3
A Power-on Reset pulse is generated on-chip
whenever V
allows the device to start in the initialized state when
V
To take advantage of the POR circuitry, tie the MCLR
pin through a resistor (1 k  to 10 k  ) to V
eliminate external RC components usually needed to
create a Power-on Reset delay. A minimum rise rate for
V
time, see
When the device starts normal operation (i.e., exits the
Reset
(voltage, frequency, temperature, etc.) must be met to
ensure operation. If these conditions are not met, the
device must be held in Reset until the operating
conditions are met.
POR events are captured by the POR bit (RCON<1>).
The state of the bit is set to ‘ 0 ’ whenever a Power-on
Reset occurs; it does not change for any other Reset
event. POR is not reset to ‘ 1 ’ by any hardware event.
To capture multiple events, the user manually resets
the bit to ‘ 1 ’ in software following any Power-on Reset.
 2011 Microchip Technology Inc.
DD
DD
is adequate for operation.
is specified (Parameter D004). For a slow rise
condition),
Master Clear Reset (MCLR)
Power-on Reset (POR)
Figure
DD
rises above a certain threshold. This
5-2.
device
operating
DD
parameters
. This will
Preliminary
PIC18F66K80 FAMILY
FIGURE 5-2:
Note 1: External Power-on Reset circuit is required
V
DD
2: R < 40 k is recommended to make sure that
3: R1  1 k will limit any current flowing into
D
only if the V
The diode, D, helps discharge the capacitor
quickly when V
the voltage drop across R does not violate
the device’s electrical specification.
MCLR from external capacitor, C, in the event
of MCLR/V
static
Overstress (EOS).
V
DD
R
C
Discharge
PP
EXTERNAL POWER-ON
RESET CIRCUIT (FOR
SLOW V
DD
pin breakdown, due to Electro-
R1
DD
power-up slope is too slow.
powers down.
(ESD)
DD
PIC18FXX80
MCLR
POWER-UP)
DS39977C-page 83
or
Electrical