PIC18F26K80-E/SP Microchip Technology Inc., PIC18F26K80-E/SP Datasheet - Page 198

• Manufacturer Part Number: PIC18F26K80-E/SP
• Description: 28 SPDIP .300IN TUBE, ECAN, 64KB FLASH, 4KB RAM, 16 MIPS, 12-BIT ADC, CTMU
• Manufacturer: Microchip Technology Inc.

Specifications of PIC18F26K80-E/SP

• A/d Inputs: 8-Channel, 12-Bit
• Comparators: 2
• Cpu Speed: 16 MIPS
• Eeprom Memory: 256 Bytes
• Input Output: 24
• Interface: I2C/SPI/UART/USART
• Memory Type: Flash
• Number Of Bits: 8
• Package Type: 28-pin SPDIP
• Programmable Memory: 64K Bytes
• Ram Size: 3.6K Bytes
• Speed: 64 MHz
• Temperature Range: –40 to 125 °C
• Timers: 2-8-bit, 3-16-bit
• Voltage, Range: 1.8-5.5 V
• Lead Free Status / Rohs Status: RoHS Compliant part

PIC18F66K80 FAMILY
11.9
PORTD can function as an 8-bit-wide Parallel Slave
Port (PSP), or microprocessor port, when control bit,
PSPMODE (PSPCON<4>), is set. The port is asyn-
chronously readable and writable by the external world
through the RD control input pin (RE0/AN5/RD) and
WR control input pin (RE1/AN6/C1OUT/WR).
The PSP can directly interface to an 8-bit micro-
processor data bus. The external microprocessor can
read or write the PORTD latch as an eight-bit latch.
Setting
RE0/AN5/RD,
RE1/AN6/C1OUT/WR to be the WR input and
RE2/AN7/C2OUT/CS to be the CS (Chip Select)
input. For this functionality, the corresponding data
direction bits of the TRISE register (TRISE<2:0>)
must be configured as inputs (= 111 ).
A write to the PSP occurs when both the CS and WR
lines are first detected low and ends when either are
detected high. The PSPIF and IBF flag bits (PIR1<7>
and PSPCON<7>, respectively) are set when the write
ends.
A read from the PSP occurs when both the CS and RD
lines are first detected low. The data in PORTD is read
out and the OBF bit (PSPCON<6>) is set. If the user
writes new data to PORTD to set OBF, the data is
immediately read out, but the OBF bit is not set.
When either the CS or RD line is detected high, the
PORTD pins return to the input state and the PSPIF bit
is set. User applications should wait for PSPIF to be set
before servicing the PSP. When this happens, the IBF
and OBF bits can be polled and the appropriate action
taken.
The timing for the control signals in Write and Read
modes is shown in
respectively.
DS39977C-page 198
Note:
Parallel Slave Port
bit,
The Parallel Slave Port is available only on
40/44-pin and 64-pin devices.
PSPMODE,
to
Figure 11-4
be
enables
the
and
RD
Figure
port
input,
11-5,
pin,
Preliminary
FIGURE 11-3:
Note: The I/O pin has protection diodes to V
One bit of PORTD
Data Bus
Set Interrupt Flag
PSPIF (PIR1<7>)
WR LATD
or
PORTD
RD PORTD
RD LATD
Data Latch
TRIS Latch
Q
D
CK
EN
EN
Q
D
PORTD AND PORTE
BLOCK DIAGRAM
(PARALLEL SLAVE PORT)
 2011 Microchip Technology Inc.
Chip Select
Read
Write
ST
ST
ST
ST
DD
and V
RDx
Pin
RD
CS
WR
SS
.