PIC18F26K80-E/SP Microchip Technology Inc., PIC18F26K80-E/SP Datasheet - Page 331

• Manufacturer Part Number: PIC18F26K80-E/SP
• Description: 28 SPDIP .300IN TUBE, ECAN, 64KB FLASH, 4KB RAM, 16 MIPS, 12-BIT ADC, CTMU
• Manufacturer: Microchip Technology Inc.

Specifications of PIC18F26K80-E/SP

• A/d Inputs: 8-Channel, 12-Bit
• Comparators: 2
• Cpu Speed: 16 MIPS
• Eeprom Memory: 256 Bytes
• Input Output: 24
• Interface: I2C/SPI/UART/USART
• Memory Type: Flash
• Number Of Bits: 8
• Package Type: 28-pin SPDIP
• Programmable Memory: 64K Bytes
• Ram Size: 3.6K Bytes
• Speed: 64 MHz
• Temperature Range: –40 to 125 °C
• Timers: 2-8-bit, 3-16-bit
• Voltage, Range: 1.8-5.5 V
• Lead Free Status / Rohs Status: RoHS Compliant part

21.4.12
An Acknowledge sequence is enabled by setting the
Acknowledge
(SSPCON2<4>). When this bit is set, the SCL pin is
pulled low and the contents of the Acknowledge data bit
are presented on the SDA pin. If the user wishes to gen-
erate an Acknowledge, then the ACKDT bit should be
cleared. If not, the user should set the ACKDT bit before
starting an Acknowledge sequence. The Baud Rate Gen-
erator then counts for one rollover period (T
SCL pin is deasserted (pulled high). When the SCL pin is
sampled high (clock arbitration), the Baud Rate Generator
counts for T
this, the ACKEN bit is automatically cleared, the Baud
Rate Generator is turned off and the MSSP module then
goes into an inactive state
21.4.12.1
If the user writes the SSPBUF when an Acknowledge
sequence is in progress, then WCOL is set and the
contents of the buffer are unchanged (the write doesn’t
occur).
FIGURE 21-25:
FIGURE 21-26:
 2011 Microchip Technology Inc.
BRG
ACKNOWLEDGE SEQUENCE
TIMING
WCOL Status Flag
SCL
SDA
; the SCL pin is then pulled low. Following
Note: T
Sequence
Note: T
Write to SSPCON2,
SSPIF
Falling edge of
9th clock
SDA
SCL
BRG
ACKNOWLEDGE SEQUENCE WAVEFORM
STOP CONDITION RECEIVE OR TRANSMIT MODE
BRG
Acknowledge sequence starts here,
ACK
(Figure
= one Baud Rate Generator period.
= one Baud Rate Generator period.
SSPIF set at
the end of receive
set PEN
Enable
ACKEN = 1, ACKDT = 0
21-25).
write to SSPCON2,
T
T
bit,
BRG
BRG
SDA asserted low before rising edge of clock
to set up Stop condition
BRG
8
D0
) and the
ACKEN
T
SCL brought high after T
BRG
Preliminary
Cleared in
software
P
T
BRG
SCL = 1 for T
after SDA sampled high. P bit (SSPSTAT<4>) is set
T
PIC18F66K80 FAMILY
BRG
ACK
21.4.13
A Stop bit is asserted on the SDA pin at the end of a
receive/transmit by setting the Stop Sequence Enable
bit,
receive/transmit, the SCL line is held low after the
falling edge of the ninth clock. When the PEN bit is set,
the master will assert the SDA line low. When the SDA
line is sampled low, the Baud Rate Generator is
reloaded and counts down to 0. When the Baud Rate
Generator times out, the SCL pin will be brought high
and one T
later, the SDA pin will be deasserted. When the SDA
pin is sampled high while SCL is high, the P bit
(SSPSTAT<4>) is set. A T
cleared and the SSPIF bit is set
21.4.13.1
If the user writes the SSPBUF when a Stop sequence
is in progress, then the WCOL bit is set and the
contents of the buffer are unchanged (the write doesn’t
occur).
T
PEN bit (SSPCON2<2>) is cleared by
BRG
hardware and the SSPIF bit is set
PEN
BRG
BRG
9
SSPIF set at the end
of Acknowledge sequence
, followed by SDA = 1 for T
BRG
STOP CONDITION TIMING
(SSPCON2<2>).
WCOL Status Flag
ACKEN automatically cleared
(Baud Rate Generator rollover count)
Cleared in
software
BRG
BRG
At
(Figure
later, the PEN bit is
DS39977C-page 331
the
21-26).
end
of
a