PIC18F26K80-E/SP Microchip Technology Inc., PIC18F26K80-E/SP Datasheet - Page 422

• Manufacturer Part Number: PIC18F26K80-E/SP
• Description: 28 SPDIP .300IN TUBE, ECAN, 64KB FLASH, 4KB RAM, 16 MIPS, 12-BIT ADC, CTMU
• Manufacturer: Microchip Technology Inc.

Specifications of PIC18F26K80-E/SP

• A/d Inputs: 8-Channel, 12-Bit
• Comparators: 2
• Cpu Speed: 16 MIPS
• Eeprom Memory: 256 Bytes
• Input Output: 24
• Interface: I2C/SPI/UART/USART
• Memory Type: Flash
• Number Of Bits: 8
• Package Type: 28-pin SPDIP
• Programmable Memory: 64K Bytes
• Ram Size: 3.6K Bytes
• Speed: 64 MHz
• Temperature Range: –40 to 125 °C
• Timers: 2-8-bit, 3-16-bit
• Voltage, Range: 1.8-5.5 V
• Lead Free Status / Rohs Status: RoHS Compliant part

PIC18F66K80 FAMILY
REGISTER 27-31: BnEIDL: TX/RX BUFFER ‘n’ EXTENDED IDENTIFIER REGISTERS,
REGISTER 27-32: BnDm: TX/RX BUFFER ‘n’ DATA FIELD BYTE ‘m’ REGISTERS IN RECEIVE MODE
REGISTER 27-33: BnDm: TX/RX BUFFER ‘n’ DATA FIELD BYTE ‘m’ REGISTERS IN TRANSMIT MODE
DS39977C-page 422
bit 7
Legend:
R = Readable bit
-n = Value at POR
bit 7-0
Note 1:
bit 7
Legend:
R = Readable bit
-n = Value at POR
bit 7-0
Note 1:
bit 7
Legend:
R = Readable bit
-n = Value at POR
bit 7-0
Note 1:
BnDm7
BnDm7
R/W-x
R/W-x
EID7
R-x
These registers are available in Mode 1 and 2 only.
These registers are available in Mode 1 and 2 only.
These registers are available in Mode 1 and 2 only.
EID<7:0>: Extended Identifier bits
BnDm<7:0>: Receive Buffer n Data Field Byte m bits (where 0  n < 3 and 0 < m < 8)
Each receive buffer has an array of registers. For example, Receive Buffer 0 has 7 registers: B0D0 to
B0D7.
BnDm<7:0>: Transmit Buffer n Data Field Byte m bits (where 0  n < 3 and 0 < m < 8)
Each transmit buffer has an array of registers. For example, Transmit Buffer 0 has 7 registers: TXB0D0
to TXB0D7.
BnDm6
BnDm6
R/W-x
R/W-x
EID6
R-x
LOW BYTE IN RECEIVE MODE [0  n  5, TXnEN (BSEL<n>) = 1]
[0  n  5, 0  m  7, TXnEN (BSEL<n>) = 0]
[0  n  5, 0  m  7, TXnEN (BSEL<n>) = 1]
W = Writable bit
W = Writable bit
W = Writable bit
‘1’ = Bit is set
‘1’ = Bit is set
‘1’ = Bit is set
BnDm5
BnDm5
R/W-x
R/W-x
EID5
R-x
BnDm4
BnDm4
FEID4
R/W-x
R/W-x
R-x
Preliminary
U = Unimplemented bit, read as ‘0’
‘0’ = Bit is cleared
U = Unimplemented bit, read as ‘0’
‘0’ = Bit is cleared
U = Unimplemented bit, read as ‘0’
‘0’ = Bit is cleared
BnDm3
BnDm3
R/W-x
R/W-x
EID3
R-x
(1)
(1)
BnDm2
BnDm2
R/W-x
R/W-x
EID2
R-x
 2011 Microchip Technology Inc.
x = Bit is unknown
x = Bit is unknown
x = Bit is unknown
BnDm1
BnDm1
R/W-x
R/W-x
EID1
R-x
(1)
BnDm0
BnDm0
R/W-x
R/W-x
EID0
R-x
bit 0
bit 0
bit 0