PIC18F26K80-E/SP Microchip Technology Inc., PIC18F26K80-E/SP Datasheet - Page 76

• Manufacturer Part Number: PIC18F26K80-E/SP
• Description: 28 SPDIP .300IN TUBE, ECAN, 64KB FLASH, 4KB RAM, 16 MIPS, 12-BIT ADC, CTMU
• Manufacturer: Microchip Technology Inc.

Specifications of PIC18F26K80-E/SP

• A/d Inputs: 8-Channel, 12-Bit
• Comparators: 2
• Cpu Speed: 16 MIPS
• Eeprom Memory: 256 Bytes
• Input Output: 24
• Interface: I2C/SPI/UART/USART
• Memory Type: Flash
• Number Of Bits: 8
• Package Type: 28-pin SPDIP
• Programmable Memory: 64K Bytes
• Ram Size: 3.6K Bytes
• Speed: 64 MHz
• Temperature Range: –40 to 125 °C
• Timers: 2-8-bit, 3-16-bit
• Voltage, Range: 1.8-5.5 V
• Lead Free Status / Rohs Status: RoHS Compliant part

PIC18F66K80 FAMILY
REGISTER 4-2:
DS39977C-page 76
bit 7
Legend:
R = Readable bit
-n = Value at POR
bit 7
bit 6
bit 5
bit 4
bit 3
bit 2
bit 1
bit 0
Note 1:
PSPMD
R/W-0
(1)
Unimplemented on devices with 28-pin devices (PIC18F2XK80, PIC18LF2XK80).
PSPMD: Peripheral Module Disable bit
1 = The PSP module is disabled. All PSP registers are held in Reset and are not writable.
0 = The PSP module is enabled
CTMUMD: PMD CTMU Disable bit
1 = The CTMU module is disabled. All CTMU registers are held in Reset and are not writable.
0 = The CTMU module is enabled
ADCMD: ADC Module Disable bit
1 = The ADC module is disabled. All ADC registers are held in Reset and are not writable.
0 = The ADC module is enabled
TMR4MD: TMR4MD Disable bit
1 = The Timer4 module is disabled. All Timer4 registers are held in Reset and are not writable.
0 = The Timer4 module is enabled
TMR3MD: TMR3MD Disable bit
1 = The Timer3 module is disabled. All Timer3 registers are held in Reset and are not writable.
0 = The Timer3 module is enabled
TMR2MD: TMR2MD Disable bit
1 = The Timer2 module is disabled. All Timer2 registers are held in Reset and are not writable.
0 = The Timer2 module is enabled
TMR1MD: TMR1MD Disable bit
1 = The Timer1 module is disabled. All Timer1 registers are held in Reset and are not writable.
0 = The Timer1 module is enabled
TMR0MD: Timer0 Module Disable bit
1 = The Timer0 module is disabled. All Timer0 registers are held in Reset and are not writable.
0 = The Timer0 module is enabled
CTMUMD
R/W-0
PMD1: PERIPHERAL MODULE DISABLE REGISTER 1
W = Writable bit
‘1’ = Bit is set
ADCMD
R/W-0
TMR4MD
R/W-0
Preliminary
(1)
U = Unimplemented bit, read as ‘0’
‘0’ = Bit is cleared
TMR3MD
R/W-0
TMR2MD
R/W-0
 2011 Microchip Technology Inc.
x = Bit is unknown
TMR1MD
R/W-0
TMR0MD
R/W-0
bit 0