PIC18F26K80-E/SP Microchip Technology Inc., PIC18F26K80-E/SP Datasheet - Page 259

• Manufacturer Part Number: PIC18F26K80-E/SP
• Description: 28 SPDIP .300IN TUBE, ECAN, 64KB FLASH, 4KB RAM, 16 MIPS, 12-BIT ADC, CTMU
• Manufacturer: Microchip Technology Inc.

Specifications of PIC18F26K80-E/SP

• A/d Inputs: 8-Channel, 12-Bit
• Comparators: 2
• Cpu Speed: 16 MIPS
• Eeprom Memory: 256 Bytes
• Input Output: 24
• Interface: I2C/SPI/UART/USART
• Memory Type: Flash
• Number Of Bits: 8
• Package Type: 28-pin SPDIP
• Programmable Memory: 64K Bytes
• Ram Size: 3.6K Bytes
• Speed: 64 MHz
• Temperature Range: –40 to 125 °C
• Timers: 2-8-bit, 3-16-bit
• Voltage, Range: 1.8-5.5 V
• Lead Free Status / Rohs Status: RoHS Compliant part

19.0
PIC18F66K80
(Capture/Compare/PWM) modules, designated CCP2
through CCP5. All the modules implement standard
Capture, Compare and Pulse-Width Modulation (PWM)
modes.
REGISTER 19-1:
 2011 Microchip Technology Inc.
bit 7
Legend:
R = Readable bit
-n = Value at POR
bit 7-6
bit 5-4
bit 3-0
Note 1:
Note:
U-0
—
2:
CAPTURE/COMPARE/PWM
(CCP) MODULES
indicates the item’s association with the
control register is named CCPxCON and
CCPxM<3:0> = 1011 will only reset the timer and not start an A/D conversion on CCPx match.
Available only on CCP2. Selected by the CANCAP (CIOCON<4>) bit. Overrides the CCP2 input pin
source.
Throughout this section, generic references
are used for register and bit names that are
the same, except for an ‘x’ variable that
specific CCP module. For example, the
refers to CCP2CON through CCP5CON.
Unimplemented: Read as ‘ 0 ’
DCxB<1:0>: PWM Duty Cycle bit 1 and bit 0 for CCPx Module bits
Capture mode:
Unused.
Compare mode:
Unused.
PWM mode:
These bits are the two Least Significant bits (bit 1 and bit 0) of the 10-bit PWM duty cycle. The eight
Most Significant bits (DCx<9:2>) of the duty cycle are found in CCPRxL.
CCPxM<3:0> : CCPx Module Mode Select bits
0000 = Capture/Compare/PWM disabled (resets CCPx module)
0001 = Reserved
0010 = Compare mode: toggle output on match (CCPxIF bit is set)
0011 = Reserved
0100 = Capture mode: every falling edge or CAN message received (time-stamp)
0101 = Capture mode: every rising edge or CAN message received (time-stamp)
0110 = Capture mode: every 4th rising edge or on every fourth CAN message received (time-stamp)
0111 = Capture mode: every 16th rising edge or on every 16th CAN message received (time-stamp)
1000 = Compare mode: initialize CCPx pin low; on compare match, force CCPx pin high (CCPxIF bit is set)
1001 = Compare mode: initialize CCPx pin high; on compare match, force CCPx pin low (CCPxIF bit is set)
1010 = Compare mode: generate software interrupt on compare match (CCPxIF bit is set, CCPx pin
1011 = Compare mode: Special Event Trigger; reset timer on CCPx match (CCPxIF bit is set)
11xx = PWM mode
family
U-0
—
CCPxCON: CCPx CONTROL REGISTER (CCP2-CCP5 MODULES)
reflects I/O state)
devices
W = Writable bit
‘1’ = Bit is set
DCxB1
R/W-0
have
four
DCxB0
R/W-0
CCP
Preliminary
U = Unimplemented bit, read as ‘0’
‘0’ = Bit is cleared
PIC18F66K80 FAMILY
CCPxM3
(1)
R/W-0
Each CCP module contains a 16-bit register that can
operate as a 16-bit Capture register, a 16-bit Compare
register or a PWM Master/Slave Duty Cycle register.
For the sake of clarity, all CCP module operation in the
following sections is described with respect to CCP2,
but is equally applicable to CCP3 through CCP5.
(1)
CCPxM2
R/W-0
(1)
x = Bit is unknown
CCPxM1
R/W-0
(2)
(2)
DS39977C-page 259
(1)
(
1
)
CCPxM0
R/W-0
bit 0
(1)
(2)
(2