PIC18F26K80-E/SP Microchip Technology Inc., PIC18F26K80-E/SP Datasheet - Page 327

• Manufacturer Part Number: PIC18F26K80-E/SP
• Description: 28 SPDIP .300IN TUBE, ECAN, 64KB FLASH, 4KB RAM, 16 MIPS, 12-BIT ADC, CTMU
• Manufacturer: Microchip Technology Inc.

Specifications of PIC18F26K80-E/SP

• A/d Inputs: 8-Channel, 12-Bit
• Comparators: 2
• Cpu Speed: 16 MIPS
• Eeprom Memory: 256 Bytes
• Input Output: 24
• Interface: I2C/SPI/UART/USART
• Memory Type: Flash
• Number Of Bits: 8
• Package Type: 28-pin SPDIP
• Programmable Memory: 64K Bytes
• Ram Size: 3.6K Bytes
• Speed: 64 MHz
• Temperature Range: –40 to 125 °C
• Timers: 2-8-bit, 3-16-bit
• Voltage, Range: 1.8-5.5 V
• Lead Free Status / Rohs Status: RoHS Compliant part

21.4.9
A Repeated Start condition occurs when the RSEN bit
(SSPCON2<1>) is programmed high and the I
module is in the Idle state. When the RSEN bit is set,
the SCL pin is asserted low. When the SCL pin is
sampled low, the Baud Rate Generator is loaded with
the contents of SSPADD<5:0> and begins counting.
The SDA pin is released (brought high) for one Baud
Rate Generator count (T
Generator times out, and if SDA is sampled high, the
SCL pin will be deasserted (brought high). When SCL
is sampled high, the Baud Rate Generator is reloaded
with the contents of SSPADD<6:0> and begins
counting. SDA and SCL must be sampled high for one
T
SDA pin (SDA = 0 ) for one T
Following this, the RSEN bit (SSPCON2<1>) will be
automatically cleared and the Baud Rate Generator will
not be reloaded, leaving the SDA pin held low. As soon
as a Start condition is detected on the SDA and SCL
pins, the S bit (SSPSTAT<3>) will be set. The SSPIF bit
will not be set until the Baud Rate Generator has timed
out.
FIGURE 21-22:
 2011 Microchip Technology Inc.
BRG
. This action is then followed by assertion of the
Write to SSPCON2
I
START CONDITION TIMING
2
C™ MASTER MODE REPEATED
on falling edge of ninth clock,
RSEN bit set by hardware
REPEATED START CONDITION WAVEFORM
BRG
SDA
SCL
occurs here:
). When the Baud Rate
BRG
end of XMIT
while SCL is high.
SDA = 1,
SCL (no change).
2
C logic
Preliminary
T
SDA = 1,
SCL = 1
BRG
PIC18F66K80 FAMILY
Immediately following the SSPIF bit getting set, the user
may write the SSPBUF with the 7-bit address in 7-bit
mode or the default first address in 10-bit mode. After the
first eight bits are transmitted and an ACK is received,
the user may then transmit an additional eight bits of
address (10-bit mode) or eight bits of data (7-bit mode).
21.4.9.1
If the user writes the SSPBUF when a Repeated Start
sequence is in progress, the WCOL is set and the
contents of the buffer are unchanged (the write doesn’t
occur).
T
BRG
Note:
Note 1: If RSEN is programmed while any other
Sr = Repeated Start
T
2: A bus collision during the Repeated Start
BRG
Because queueing of events is not
allowed, writing of the lower 5 bits of
SSPCON2 is disabled until the Repeated
Start condition is complete.
event is in progress, it will not take effect.
condition occurs if:
• SDA is sampled low when SCL goes
• SCL goes low before SDA is
At completion of Start bit,
hardware clears RSEN bit
WCOL Status Flag
S bit set by hardware
from low-to-high.
asserted low. This may indicate that
another master is attempting to
transmit a data ‘ 1 ’.
and sets SSPIF
Write to SSPBUF occurs here
T
BRG
1st bit
T
BRG
DS39977C-page 327