PIC18F26K80-E/SP Microchip Technology Inc., PIC18F26K80-E/SP Datasheet - Page 476

• Manufacturer Part Number: PIC18F26K80-E/SP
• Description: 28 SPDIP .300IN TUBE, ECAN, 64KB FLASH, 4KB RAM, 16 MIPS, 12-BIT ADC, CTMU
• Manufacturer: Microchip Technology Inc.

Specifications of PIC18F26K80-E/SP

• A/d Inputs: 8-Channel, 12-Bit
• Comparators: 2
• Cpu Speed: 16 MIPS
• Eeprom Memory: 256 Bytes
• Input Output: 24
• Interface: I2C/SPI/UART/USART
• Memory Type: Flash
• Number Of Bits: 8
• Package Type: 28-pin SPDIP
• Programmable Memory: 64K Bytes
• Ram Size: 3.6K Bytes
• Speed: 64 MHz
• Temperature Range: –40 to 125 °C
• Timers: 2-8-bit, 3-16-bit
• Voltage, Range: 1.8-5.5 V
• Lead Free Status / Rohs Status: RoHS Compliant part

PIC18F66K80 FAMILY
28.2
For the PIC18F66K80 family of devices, the WDT is
driven by the LF-INTOSC source. When the WDT is
enabled, the clock source is also enabled. The nominal
WDT period is 4 ms and has the same stability as the
LF-INTOSC oscillator.
The 4 ms period of the WDT is multiplied by a 16-bit
postscaler. Any output of the WDT postscaler is
selected by a multiplexer, controlled by bits in
Configuration Register 2H. Available periods range
from 4 ms to 4,194 seconds (about one hour). The
WDT and postscaler are cleared when any of the
following events occur: a SLEEP or CLRWDT instruction
is executed, the IRCF bits (OSCCON<6:4>) are
changed or a clock failure has occurred.
FIGURE 28-1:
DS39977C-page 476
WDT Disabled in Hardware,
WDT Enabled only while
Device Active, Disabled
WDTEN1
WDTEN0
Watchdog Timer (WDT)
WDT Controlled with
SWDTEN bit Setting
Change on IRCF bits
SWDTEN Disabled
SWDTEN Disabled
All Device Resets
INTOSC Source
WDT Enabled,
WDTPS<3:0>
CLRWDT
WDT BLOCK DIAGRAM
Sleep
Enable WDT
WDT Counter
 128
Preliminary
4
Programmable Postscaler
1:1 to 1:1,048,576
The WDT can be operated in one of four modes as
determined by WDTEN<1:0> (CONFIG2H<1:0>. The
four modes are:
• WDT Enabled
• WDT Disabled
• WDT under Software Control,
• WDT
SWDTEN (WDTCON<0>)
- Enabled during normal operation
- Disabled during Sleep
Note 1: The CLRWDT and SLEEP instructions
2: Changing the setting of the IRCF bits
3: When a CLRWDT instruction is executed,
clear the WDT and postscaler counts
when executed.
(OSCCON<6:4>) clears the WDT and
postscaler counts.
the postscaler count will be cleared.
INTOSC Source
WDTEN<1:0>
SWDTEN
Reset
 2011 Microchip Technology Inc.
Wake-up from
Power-Manage
Modes
Enable WDT
WDT
Reset