PIC18F26K80-E/SP Microchip Technology Inc., PIC18F26K80-E/SP Datasheet - Page 265

• Manufacturer Part Number: PIC18F26K80-E/SP
• Description: 28 SPDIP .300IN TUBE, ECAN, 64KB FLASH, 4KB RAM, 16 MIPS, 12-BIT ADC, CTMU
• Manufacturer: Microchip Technology Inc.

Specifications of PIC18F26K80-E/SP

• A/d Inputs: 8-Channel, 12-Bit
• Comparators: 2
• Cpu Speed: 16 MIPS
• Eeprom Memory: 256 Bytes
• Input Output: 24
• Interface: I2C/SPI/UART/USART
• Memory Type: Flash
• Number Of Bits: 8
• Package Type: 28-pin SPDIP
• Programmable Memory: 64K Bytes
• Ram Size: 3.6K Bytes
• Speed: 64 MHz
• Temperature Range: –40 to 125 °C
• Timers: 2-8-bit, 3-16-bit
• Voltage, Range: 1.8-5.5 V
• Lead Free Status / Rohs Status: RoHS Compliant part

19.3
In Compare mode, the 16-bit CCPRx register value is
constantly compared against the Timer register pair
value selected in the CCPTMR register. When a match
occurs, the CCPx pin can be:
• Driven high
• Driven low
• Toggled (high-to-low or low-to-high)
• Unchanged (that is, reflecting the state of the I/O
The action on the pin is based on the value of the mode
select bits (CCPxM<3:0>). At the same time, the
interrupt flag bit, CCPxIF, is set.
Figure 19-2
19.3.1
The user must configure the CCPx pin as an output by
clearing the appropriate TRIS bit.
19.3.2
If the CCPx module is using the compare feature in
conjunction with any of the Timer1/3 timers, the timers
must be running in Timer mode or Synchronized
Counter mode. In Asynchronous Counter mode, the
compare operation may not work.
 2011 Microchip Technology Inc.
latch)
Note:
Note:
Compare Mode
gives the Compare mode block diagram
CCP PIN CONFIGURATION
Clearing the CCPxCON register will force
the corresponding CCPx compare output
latch (depending on device configuration)
to the default low level. This is not the
PORTx data latch.
TIMER1/3 MODE SELECTION
Details of the timer assignments for the
CCPx modules are given in
Table
19-2.
Preliminary
PIC18F66K80 FAMILY
19.3.3
When the Generate Software Interrupt mode is chosen
(CCPxM<3:0> = 1010 ), the CCPx pin is not affected.
Only a CCP interrupt is generated, if enabled, and the
CCPxIE bit is set.
19.3.4
All CCP modules are equipped with a Special Event
Trigger. This is an internal hardware signal generated
in Compare mode to trigger actions by other modules.
The Special Event Trigger is enabled by selecting
the Compare Special Event Trigger mode bits
(CCPxM<3:0> = 1011 ).
For either CCPx module, the Special Event Trigger
resets the Timer register pair for whichever timer
resource is currently assigned as the module’s time
base. This allows the CCPRx registers to serve as a
programmable Period register for either timer.
SOFTWARE INTERRUPT MODE
SPECIAL EVENT TRIGGER
DS39977C-page 265