PIC18F26K80-E/SP Microchip Technology Inc., PIC18F26K80-E/SP Datasheet - Page 374

• Manufacturer Part Number: PIC18F26K80-E/SP
• Description: 28 SPDIP .300IN TUBE, ECAN, 64KB FLASH, 4KB RAM, 16 MIPS, 12-BIT ADC, CTMU
• Manufacturer: Microchip Technology Inc.

Specifications of PIC18F26K80-E/SP

• A/d Inputs: 8-Channel, 12-Bit
• Comparators: 2
• Cpu Speed: 16 MIPS
• Eeprom Memory: 256 Bytes
• Input Output: 24
• Interface: I2C/SPI/UART/USART
• Memory Type: Flash
• Number Of Bits: 8
• Package Type: 28-pin SPDIP
• Programmable Memory: 64K Bytes
• Ram Size: 3.6K Bytes
• Speed: 64 MHz
• Temperature Range: –40 to 125 °C
• Timers: 2-8-bit, 3-16-bit
• Voltage, Range: 1.8-5.5 V
• Lead Free Status / Rohs Status: RoHS Compliant part

PIC18F66K80 FAMILY
23.7
Figure 23-6
after the GO/DONE bit has been set and the
ACQT<2:0> bits are cleared. A conversion is started
after the following instruction to allow entry into Sleep
mode before the conversion begins.
Figure 23-7
after the GO/DONE bit has been set, the ACQT<2:0>
bits set to ‘ 010 ’ and a 4 T
Clearing the GO/DONE bit during a conversion will
abort the current conversion. The A/D Result register
pair will NOT be updated with the partially completed
A/D
FIGURE 23-6:
FIGURE 23-7:
DS39977C-page 374
(Holding capacitor continues
acquiring input)
Set GO/DONE bit
1
conversion
A/D Conversions
T
T
Set GO/DONE bit
CY
Automatic
Acquisition
Time
ACQT
Holding capacitor is disconnected from analog input (typically 100 ns)
shows the operation of the A/D Converter
shows the operation of the A/D Converter
2
- T
AD
Cycles
Conversion starts
T
3
AD
sample.
A/D CONVERSION T
A/D CONVERSION T
1 T
AD
4
b11
AD
acquisition time selected.
2 T
Conversion starts
(Holding capacitor is disconnected)
1
This
b10
AD
3 T
b11
2
AD
means
Next Q4: ADRESH:ADRESL is loaded, GO/DONE bit is cleared,
b9
Next Q4: ADRESH:ADRESL is loaded, GO/DONE bit is cleared,
4 T
b10
AD
AD
3
AD
b8
CYCLES (ACQT<2:0> = 000, T
CYCLES (ACQT<2:0> = 010, T
5 T
Preliminary
ADIF bit is set, holding capacitor is reconnected to analog input.
the
ADIF bit is set, holding capacitor is connected to analog input.
b9
4
AD
b7
6 T
T
5
b8
AD
AD
b6
7 T
Cycles
ADRESH:ADRESL registers will continue to contain
the value of the last completed conversion (or the last
value written to the ADRESH:ADRESL registers).
After the A/D conversion is completed or aborted, a
2 T
started. After this wait, acquisition on the selected
channel is automatically started.
Note:
b7
AD
6
AD
b5
wait is required before the next acquisition can be
8
b6
T
7
AD
b4
The GO/DONE bit should NOT be set in
the same instruction that turns on the A/D.
9 T
b5
8
AD
b3
10
ACQ
ACQ
T
b4
9
AD
 2011 Microchip Technology Inc.
b2
= 0)
= 4 T
11
T
10
b3
AD
AD
b1
12
)
T
b2
11
AD
b0
13
12
b1
13
b0