PIC18F26K80-E/SP Microchip Technology Inc., PIC18F26K80-E/SP Datasheet - Page 297

• Manufacturer Part Number: PIC18F26K80-E/SP
• Description: 28 SPDIP .300IN TUBE, ECAN, 64KB FLASH, 4KB RAM, 16 MIPS, 12-BIT ADC, CTMU
• Manufacturer: Microchip Technology Inc.

Specifications of PIC18F26K80-E/SP

• A/d Inputs: 8-Channel, 12-Bit
• Comparators: 2
• Cpu Speed: 16 MIPS
• Eeprom Memory: 256 Bytes
• Input Output: 24
• Interface: I2C/SPI/UART/USART
• Memory Type: Flash
• Number Of Bits: 8
• Package Type: 28-pin SPDIP
• Programmable Memory: 64K Bytes
• Ram Size: 3.6K Bytes
• Speed: 64 MHz
• Temperature Range: –40 to 125 °C
• Timers: 2-8-bit, 3-16-bit
• Voltage, Range: 1.8-5.5 V
• Lead Free Status / Rohs Status: RoHS Compliant part

21.3.4
To enable the serial port, MSSP Enable bit, SSPEN
(SSPCON1<5>), must be set. To reset or reconfigure
SPI mode, clear the SSPEN bit, reinitialize the
SSPCON registers and then set the SSPEN bit. This
configures the SDI, SDO, SCK and SS pins as serial
port pins. For the pins to behave as the serial port func-
tion, some must have their data direction bits (in the
TRIS register) appropriately programmed as follows:
• SDI is automatically controlled by the SPI module
• SDO must have the TRISC<5> bit cleared
• SCK (Master mode) must have the TRISC<3> bit
• SCK (Slave mode) must have the TRISC<3> bit
• SS must have the TRISA<5> bit set
Any serial port function that is not desired may be
overridden by programming the corresponding Data
Direction (TRIS) register to the opposite value.
FIGURE 21-2:
 2011 Microchip Technology Inc.
cleared
set
SPI Master SSPM<3:0> =
ENABLING SPI I/O
MSb
PROCESSOR 1
Serial Input Buffer
SPI MASTER/SLAVE CONNECTION
Shift Register
(SSPBUF)
(SSPSR)
00xx
LSb
b
SDO
SCK
SDI
Preliminary
Serial Clock
PIC18F66K80 FAMILY
21.3.5
Figure 21-2
microcontrollers. The master controller (Processor 1)
initiates the data transfer by sending the SCK signal.
Data is shifted out of both shift registers on their pro-
grammed clock edge and latched on the opposite edge
of the clock. Both processors should be programmed to
the same Clock Polarity (CKP), then both controllers
would send and receive data at the same time.
Whether the data is meaningful (or dummy data)
depends on the application software. This leads to
three scenarios for data transmission:
• Master sends data  –  Slave sends dummy data
• Master sends data  –  Slave sends data
• Master sends dummy data  –  Slave sends data
SDO
SCK
SDI
TYPICAL CONNECTION
shows a typical connection between two
SPI Slave SSPM<3:0> =
MSb
Serial Input Buffer
Shift Register
PROCESSOR 2
(SSPBUF)
(SSPSR)
LSb
DS39977C-page 297
010x
b