PIC18F26K80-E/SP Microchip Technology Inc., PIC18F26K80-E/SP Datasheet - Page 263

• Manufacturer Part Number: PIC18F26K80-E/SP
• Description: 28 SPDIP .300IN TUBE, ECAN, 64KB FLASH, 4KB RAM, 16 MIPS, 12-BIT ADC, CTMU
• Manufacturer: Microchip Technology Inc.

Specifications of PIC18F26K80-E/SP

• A/d Inputs: 8-Channel, 12-Bit
• Comparators: 2
• Cpu Speed: 16 MIPS
• Eeprom Memory: 256 Bytes
• Input Output: 24
• Interface: I2C/SPI/UART/USART
• Memory Type: Flash
• Number Of Bits: 8
• Package Type: 28-pin SPDIP
• Programmable Memory: 64K Bytes
• Ram Size: 3.6K Bytes
• Speed: 64 MHz
• Temperature Range: –40 to 125 °C
• Timers: 2-8-bit, 3-16-bit
• Voltage, Range: 1.8-5.5 V
• Lead Free Status / Rohs Status: RoHS Compliant part

19.2
In Capture mode, the CCPRxH:CCPRxL register pair
captures the 16-bit value of the Timer register selected
in the CCPTMRS when an event occurs on the CCPx
pin. An event is defined as one of the following:
• Every falling edge
• Every rising edge
• Every 4th rising edge
• Every 16th rising edge
The event is selected by the mode select bits,
CCPxM<3:0> (CCPxCON<3:0>). When a capture is
made, the interrupt request flag bit, CCPxIF (PIR4<x>),
is set; it must be cleared in software. If another capture
occurs before the value in CCPRx is read, the old
captured value is overwritten by the new captured
value.
Figure 19-1
FIGURE 19-1:
 2011 Microchip Technology Inc.
Note:
Note:
Capture Mode
For CCP2 only, the Capture mode can use
the CCP2 input pin as the capture trigger
for CCP2 or the input can function as a
time-stamp through the CAN module. The
CAN module provides the necessary
control and trigger signals.
shows the Capture mode block diagram.
CCP3 Pin
CCP4 Pin
This block diagram uses CCP3 and CCP4, and their appropriate timers as an example. For details on all of
the CCP modules and their timer assignments, see
CAPTURE MODE OPERATION BLOCK DIAGRAM
CCP3CON<3:0>
CCP4CON<3:0>
Prescaler
 1, 4, 16
Prescaler
 1, 4, 16
Q1:Q4
4
Edge Detect
Edge Detect
4
4
and
and
Preliminary
Set CCP4IF
Set CCP3IF
PIC18F66K80 FAMILY
C4TSEL
C3TSEL
C3TSEL
C4TSEL
Table
19.2.1
In Capture mode, the appropriate CCPx pin should be
configured as an input by setting the corresponding
TRIS direction bit.
19.2.2
For the available timers (1/3) to be used for the capture
feature, the used timers must be running in Timer mode
or Synchronized Counter mode. In Asynchronous
Counter mode, the capture operation may not work.
The timer to be used with each CCP module is selected
in the CCPTMRS register. (See
Modules and Timer Resources”
Details of the timer assignments for the CCP modules
are given in
19-2.
CCP PIN CONFIGURATION
TIMER1/3 MODE SELECTION
Table
19-2.
TMR3
Enable
TMR1
Enable
TMR3
Enable
TMR1
Enable
CCPR3H
CCPR4H
TMR3H
TMR1H
TMR3H
TMR1H
CCPR3L
CCPR4L
Section 19.1.1 “CCP
.)
TMR1L
TMR3L
TMR3L
TMR1L
DS39977C-page 263