PIC18F26K80-E/SP Microchip Technology Inc., PIC18F26K80-E/SP Datasheet - Page 191

• Manufacturer Part Number: PIC18F26K80-E/SP
• Description: 28 SPDIP .300IN TUBE, ECAN, 64KB FLASH, 4KB RAM, 16 MIPS, 12-BIT ADC, CTMU
• Manufacturer: Microchip Technology Inc.

Specifications of PIC18F26K80-E/SP

• A/d Inputs: 8-Channel, 12-Bit
• Comparators: 2
• Cpu Speed: 16 MIPS
• Eeprom Memory: 256 Bytes
• Input Output: 24
• Interface: I2C/SPI/UART/USART
• Memory Type: Flash
• Number Of Bits: 8
• Package Type: 28-pin SPDIP
• Programmable Memory: 64K Bytes
• Ram Size: 3.6K Bytes
• Speed: 64 MHz
• Temperature Range: –40 to 125 °C
• Timers: 2-8-bit, 3-16-bit
• Voltage, Range: 1.8-5.5 V
• Lead Free Status / Rohs Status: RoHS Compliant part

TABLE 11-7:
 2011 Microchip Technology Inc.
RD0/C1INA/
PSP0
RD1/C1INB/
PSP1
RD2/C2INA/
PSP2
RD3/C2INB/
CTMUI/PSP3
RD4/ECCP1/
P1A/PSP4
RD5/P1B/PSP5
RD6/TX2/CK2
P1C/PSP6
Legend:
Note 1:
Pin Name
O = Output, I = Input, ANA = Analog Signal, DIG = CMOS Output, ST = Schmitt Trigger Buffer Input,
x = Don’t care (TRIS bit does not affect port direction or is overridden for this option)
Pin assignment for 40 and 44-pin devices (PIC18F4XK80).
Function
PORTD FUNCTIONS
C1INB
PSP1
ECCP1
CTMUI
C1INA
RD1
C2INA
C2INB
CK2
TX2
PSP0
PSP2
PSP3
PSP4
PSP5
PSP6
RD0
RD2
RD3
RD4
RD5
RD6
P1C
P1A
P1B
(1)
(1)
(1)
(1)
(1)
Setting
TRIS
0
1
1
x
0
1
1
x
0
1
1
x
0
1
1
x
x
0
1
0
1
0
x
0
1
0
x
0
1
0
0
1
0
x
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
O
O
O
O
O
O
O
O
O
O
O
O
O
I
I
I
I
I
I
I
I
I
I
I
I
I
I
I/O Type
ANA
ANA
ANA
ANA
DIG
DIG
DIG
DIG
DIG
DIG
DIG
DIG
DIG
DIG
DIG
DIG
DIG
ST
ST
ST
ST
ST
ST
ST
ST
ST
ST
ST
ST
ST
ST
ST
ST
—
Preliminary
LATD<0> data output.
PORTD<0> data input.
Comparator 1 Input A.
Parallel Slave Port data.
LATD<1> data output.
PORTD<1> data input.
Comparator 1 Input B.
Parallel Slave Port data.
LATD<2> data output.
PORTD<2> data input.
Comparator 2 Input A.
Parallel Slave Port data.
LATD<3> data output.
PORTD<3> data input.
Comparator 2 Input B.
CTMU pulse generator charger for the C2INB comparator input.
Parallel Slave Port data.
LATD<4> data output.
PORTD<4> data input.
ECCP1 compare output and ECCP1 PWM output. Takes priority over
port data.
ECCP1 capture input.
ECCP1 Enhanced PWM output, Channel A. May be configured for
tri-state during Enhanced PWM shutdown events. Takes priority over
port data.
Parallel Slave Port data.
LATD<5> data output.
PORTD<5> data input.
ECCP1 Enhanced PWM output, Channel B. May be configured for
tri-state during Enhanced PWM shutdown events. Takes priority over
port data.
Parallel Slave Port data.
LATD<6> data output.
PORTD<6> data input.
Asynchronous serial data output (EUSART module); takes priority over
port data.
Synchronous serial clock output (EUSART module); user must
configure as an input.
Synchronous serial clock input (EUSART module); user must configure
as an input.
ECCP1 Enhanced PWM output, Channel C. May be configured for
tri-state during Enhanced PWM.
Parallel Slave Port data.
PIC18F66K80 FAMILY
Description
DS39977C-page 191