PIC18F26K80-E/SP Microchip Technology Inc., PIC18F26K80-E/SP Datasheet - Page 503
PIC18F26K80-E/SP
Manufacturer Part Number
PIC18F26K80-E/SP
Description
28 SPDIP .300IN TUBE, ECAN, 64KB FLASH, 4KB RAM, 16 MIPS, 12-BIT ADC, CTMU
Manufacturer
Microchip Technology Inc.
Datasheet
1.PIC18F46K80-IPT.pdf
(628 pages)
Specifications of PIC18F26K80-E/SP
A/d Inputs
8-Channel, 12-Bit
Comparators
2
Cpu Speed
16 MIPS
Eeprom Memory
256 Bytes
Input Output
24
Interface
I2C/SPI/UART/USART
Memory Type
Flash
Number Of Bits
8
Package Type
28-pin SPDIP
Programmable Memory
64K Bytes
Ram Size
3.6K Bytes
Speed
64 MHz
Temperature Range
–40 to 125 °C
Timers
2-8-bit, 3-16-bit
Voltage, Range
1.8-5.5 V
Lead Free Status / Rohs Status
RoHS Compliant part
Available stocks
Company
Part Number
Manufacturer
Quantity
Price
Company:
Part Number:
PIC18F26K80-E/SP
Manufacturer:
SILICON
Quantity:
210
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CLRF
Syntax:
Operands:
Operation:
Status Affected:
Encoding:
Description:
Words:
Cycles:
Example:
2011 Microchip Technology Inc.
Q Cycle Activity:
Before Instruction
After Instruction
Decode
FLAG_REG
FLAG_REG
Q1
register ‘f’
Clear f
CLRF
0 f 255
a [0,1]
000h f,
1 Z
Z
Clears the contents of the specified
register.
If ‘a’ is ‘ 0 ’, the Access Bank is selected.
If ‘a’ is ‘ 1 ’, the BSR is used to select the
GPR bank.
If ‘a’ is ‘ 0 ’ and the extended instruction
set is enabled, this instruction operates
in Indexed Literal Offset Addressing
mode whenever f 95 (5Fh). See
Section 29.2.3 “Byte-Oriented and
Bit-Oriented Instructions in Indexed
Literal Offset Mode”
1
1
CLRF
Read
0110
Q2
=
=
f {,a}
5Ah
00h
101a
FLAG_REG,1
Process
Data
Q3
ffff
for details.
register ‘f’
Write
Q4
ffff
Preliminary
PIC18F66K80 FAMILY
CLRWDT
Syntax:
Operands:
Operation:
Status Affected:
Encoding:
Description:
Words:
Cycles:
Example:
Q Cycle Activity:
Before Instruction
After Instruction
Decode
WDT Counter
WDT Counter
WDT Postscaler
TO
PD
Q1
operation
Clear Watchdog Timer
CLRWDT
None
000h WDT,
000h WDT postscaler,
1 TO,
1 PD
TO, PD
CLRWDT instruction resets the
Watchdog Timer. It also resets the
postscaler of the WDT. Status bits, TO
and PD, are set.
1
1
CLRWDT
0000
No
Q2
=
=
=
=
=
0000
?
00h
0
1
1
Process
Data
Q3
DS39977C-page 503
0000
operation
No
Q4
0100
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