PIC18F26K80-E/SP Microchip Technology Inc., PIC18F26K80-E/SP Datasheet - Page 308

• Manufacturer Part Number: PIC18F26K80-E/SP
• Description: 28 SPDIP .300IN TUBE, ECAN, 64KB FLASH, 4KB RAM, 16 MIPS, 12-BIT ADC, CTMU
• Manufacturer: Microchip Technology Inc.

Specifications of PIC18F26K80-E/SP

• A/d Inputs: 8-Channel, 12-Bit
• Comparators: 2
• Cpu Speed: 16 MIPS
• Eeprom Memory: 256 Bytes
• Input Output: 24
• Interface: I2C/SPI/UART/USART
• Memory Type: Flash
• Number Of Bits: 8
• Package Type: 28-pin SPDIP
• Programmable Memory: 64K Bytes
• Ram Size: 3.6K Bytes
• Speed: 64 MHz
• Temperature Range: –40 to 125 °C
• Timers: 2-8-bit, 3-16-bit
• Voltage, Range: 1.8-5.5 V
• Lead Free Status / Rohs Status: RoHS Compliant part

PIC18F66K80 FAMILY
21.4.3.2
Masking an address bit causes that bit to become a
“don’t care”. When one address bit is masked, two
addresses will be Acknowledged and cause an
interrupt. It is possible to mask more than one address
bit at a time, which greatly expands the number of
addresses Acknowledged.
The I
masking is used or not. However, when address
masking is used, the I
multiple addresses and cause interrupts. When this
occurs, it is necessary to determine which address
caused the interrupt by checking the SSPBUF.
The PIC18F66K80 family of devices is capable of using
two different Address Masking modes in I
operation: 5-Bit Address Masking and 7-Bit Address
Masking. The Masking mode is selected at device
configuration using the MSSPMSK Configuration bit.
The default device configuration is 7-Bit Address
Masking.
Both Masking modes, in turn, support address masking
of 7-bit and 10-bit addresses. The combination of
Masking modes and addresses provide different
ranges of Acknowledgable addresses for each
combination.
While both Masking modes function in roughly the
same manner, the way they use address masks are
different.
21.4.3.3
As the name implies, 5-Bit Address Masking mode uses
an address mask of up to 5 bits to create a range of
addresses to be Acknowledged, using bits, 5 through 1,
EXAMPLE 21-2:
DS39977C-page 308
7-Bit Addressing:
10-Bit Addressing:
2
C slave behaves the same way, whether address
SSPADD<7:1>= A0h ( 1010000 ) (SSPADD<0> is assumed to be ‘ 0 ’)
ADMSK<5:1> = 00111
Addresses Acknowledged: A0h, A2h, A4h, A6h, A8h, AAh, ACh, AEh
SSPADD<7:0> = A0h ( 10100000 ) (The two MSb of the address are ignored in this example, since they
are not affected by masking)
ADMSK<5:1> = 00111
Addresses Acknowledged: A0h, A1h, A2h, A3h, A4h, A5h, A6h, A7h, A8h, A9h, AAh, ABh, ACh, ADh,
AEh, AFh
Address Masking Modes
5-Bit Address Masking Mode
ADDRESS MASKING EXAMPLES IN 5-BIT MASKING MODE
2
C slave can Acknowledge
2
C slave
Preliminary
of the incoming address. This allows the module to
Acknowledge up to 31 addresses when using 7-bit
addressing, or 63 addresses with 10-bit addressing
(see
when the MSSPMSK Configuration bit is programmed
(‘ 0 ’).
The address mask in this mode is stored in the
SSPCON2 register, which stops functioning as a con-
trol register in I
Addressing mode, address mask bits, ADMSK<5:1>
(SSPCON2<5:1>), mask the corresponding address
bits in the SSPADD register. For any ADMSK bits that
are set (ADMSK<n> = 1 ), the corresponding address
bit is ignored (SSPADD<n> = x ). For the module to
issue an address Acknowledge, it is sufficient to match
only on addresses that do not have an active address
mask.
In 10-Bit Addressing mode, bits, ADMSK<5:2>, mask
the corresponding address bits in the SSPADD regis-
ter. In addition, ADMSK1 simultaneously masks the two
LSbs of the address (SSPADD<1:0>). For any ADMSK
bits that are active (ADMSK<n> = 1 ), the correspond-
ing address bit is ignored (SPxADD<n> = x ). Also note
that although in 10-Bit Addressing mode, the upper
address bits reuse part of the SSPADD register bits.
The address mask bits do not interact with those bits;
they only affect the lower address bits.
Note 1: ADMSK1 masks the two Least Significant
Example
2: The two Most Significant bits of the
bits of the address.
address are not affected by address
masking.
21-2). This Masking mode is selected
2
C Slave mode
 2011 Microchip Technology Inc.
(Register
21-6). In 7-Bit