MC68EC000EI12 Freescale Semiconductor, MC68EC000EI12 Datasheet - Page 99

• Manufacturer Part Number: MC68EC000EI12
• Description: IC MPU 32BIT 12MHZ 68-PLCC
• Manufacturer: Freescale Semiconductor
• Series: 68K - M680X0r

Specifications of MC68EC000EI12

• Processor Type: M680x0 32-Bit
• Speed: 12MHz
• Voltage: 3.3V, 5V
• Mounting Type: Surface Mount
• Package / Case: 68-PLCC
• Core Size: 32 Bit
• Cpu Speed: 12MHz
• Digital Ic Case Style: PLCC
• No. Of Pins: 68
• Supply Voltage Range: 3V To 3.6V
• Operating Temperature Range: 0°C To +70°C
• Filter Terminals: SMD
• Rohs Compliant: Yes
• Clock Frequency: 12MHz
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Features: -

Instruction Set Summary
3.6.1 Underflow, Round, Overflow
During the calculation of an arithmetic result, the FPU arithmetic logic unit (ALU) has more
precision and range than the 80-bit extended precision format. However, the final result of
these operations is an extended-precision floating-point value. In some cases, an
intermediate result becomes either smaller or larger than can be represented in extended
precision. Also, the operation can generate a larger exponent or more bits of precision than
can be represented in the chosen rounding precision. For these reasons, every arithmetic
instruction ends by rounding the result and checking for overflow and underflow.
At the completion of an arithmetic operation, the intermediate result is checked to see if it is
too small to be represented as a normalized number in the selected precision. If so, the
underflow (UNFL) bit is set in the FPSR EXC byte. It is also denormalized unless
denormalization provides a zero value. Denormalizing a number causes a loss of accuracy,
but a zero is not returned unless absolutely necessary. If a number is grossly underflowed,
the FPU returns a zero or the smallest denormalized number with the correct sign,
depending on the rounding mode in effect.
If no underflow occurs, the intermediate result is rounded according to the user-selected
rounding precision and rounding mode. After rounding, the inexact bit (INEX2) is set
appropriately. Lastly, the magnitude of the result is checked to see if it is too large to be
represented in the current rounding precision. If so, the overflow (OVFL) bit is set and a
correctly signed infinity or correctly signed largest normalized number is returned,
depending on the rounding mode in effect.
3.6.2 Conditional Testing
Unlike the integer arithmetic condition codes, an instruction either always sets the floating-
point condition codes in the same way or it does not change them at all. Therefore, the
instruction descriptions do not include floating-point condition code settings. The following
paragraphs describe how floating-point condition codes are set for all instructions that
modify condition codes.
The condition code bits differ slightly from the integer condition codes. Unlike the operation
type dependent integer condition codes, examining the result at the end of the operation
sets or clears the floating-point condition codes accordingly. The M68000 family integer
condition codes bits N and Z have this characteristic, but the V and C bits are set differently
for different instructions. The data type of the operation’s result determines how the four
condition code bits are set. Table 3-22 lists the condition code bit setting for each data type.
Loading the FPCC with one of the other combinations and executing a conditional
instruction can produce an unexpected branch condition.
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M68000 FAMILY PROGRAMMER’S REFERENCE MANUAL
MOTOROLA