MC68EC000EI12 Freescale Semiconductor, MC68EC000EI12 Datasheet - Page 449

• Manufacturer Part Number: MC68EC000EI12
• Description: IC MPU 32BIT 12MHZ 68-PLCC
• Manufacturer: Freescale Semiconductor
• Series: 68K - M680X0r

Specifications of MC68EC000EI12

• Processor Type: M680x0 32-Bit
• Speed: 12MHz
• Voltage: 3.3V, 5V
• Mounting Type: Surface Mount
• Package / Case: 68-PLCC
• Core Size: 32 Bit
• Cpu Speed: 12MHz
• Digital Ic Case Style: PLCC
• No. Of Pins: 68
• Supply Voltage Range: 3V To 3.6V
• Operating Temperature Range: 0°C To +70°C
• Filter Terminals: SMD
• Rohs Compliant: Yes
• Clock Frequency: 12MHz
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Features: -

FTST
Operation:
Assembler
Syntax:
Attributes:
Description: Converts the source operand to extended precision (if necessary) and sets the
Operation Table: The contents of this table differfromtheother operation tables. A letter in
Floating-Point Status Register:
MOTOROLA
NOTE: If the source operand is a NAN, set the NAN condition code bit. If the source
condition code bits according to the data type of the result.
an entry of this table indicates that the designated condition code bit is always set by
the FTST operation. All unspecified condition code bits are cleared during the
operation.
Condition Codes:
Quotient Byte:
Exception Byte:
Accrued Exception Byte:
DESTINATION
operand is an SNAN, set the SNAN bit in the floating-point status register
exception byte
Result
M68000 FAMILY PROGRAMMER’S REFERENCE MANUAL
Condition Codes for Operand
FTST. < fmt > < ea >
FTST.X FPm
Format = (Byte, Word, Long, Single, Double, Extended, Packed)
+
none
Test Floating-Point Operand
In Range
Affected as described in 3.6.2 Conditional Testing.
Not affected.
BSUN
SNAN
OPERR
OVFL
UNFL
DZ
INEX2
INEX1
Affected as described in exception processing in the appro-
priate user’s manual.
(MC6888X, MC68040)
N Z
– +
Cleared
Refer to 1.6.5 Not-A-Numbers.
Cleared
Cleared
Cleared
Cleared
Cleared
If < fmt > is packed, refer to exception
processing in the appropriate user’s manual;
cleared otherwise.
SOURCE
FPCC
Zero
NZ I
– +
Floating Point Instructions
Infinity
FTST
NI
–
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