MC68EC000EI12 Freescale Semiconductor, MC68EC000EI12 Datasheet - Page 16

• Manufacturer Part Number: MC68EC000EI12
• Description: IC MPU 32BIT 12MHZ 68-PLCC
• Manufacturer: Freescale Semiconductor
• Series: 68K - M680X0r

Specifications of MC68EC000EI12

• Processor Type: M680x0 32-Bit
• Speed: 12MHz
• Voltage: 3.3V, 5V
• Mounting Type: Surface Mount
• Package / Case: 68-PLCC
• Core Size: 32 Bit
• Cpu Speed: 12MHz
• Digital Ic Case Style: PLCC
• No. Of Pins: 68
• Supply Voltage Range: 3V To 3.6V
• Operating Temperature Range: 0°C To +70°C
• Filter Terminals: SMD
• Rohs Compliant: Yes
• Clock Frequency: 12MHz
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Features: -

1.2.2 Floating-Point Control Register (FPCR)
The FPCR (see Figure 1-3) contains an exception enable (ENABLE) byte and a mode
control (MODE) byte. The user can read or write to the FPCR. Motorola reserves bits 31 –
16 for future definition; these bits are always read as zero and are ignored during write
operations. The reset function or a restore operation of the null state clears the FPCR. When
cleared, this register provides the IEEE 754 Standard for Binary Floating-Point Arithmetic
defaults.
1.2.2.1 EXCEPTION ENABLE BYTE. Each bit of the ENABLE byte (see Figure 1-3)
corresponds to a floating-point exception class. The user can separately enable traps for
each class of floating-point exceptions.
1.2.2.2 MODE CONTROL BYTE. MODE (see Figure 1-3) controls the user- selectable
rounding modes and precisions. Zeros in this byte select the IEEE 754 standard defaults.
The rounding mode (RND) field specifies how inexact results are rounded, and the rounding
precision (PREC) field selects the boundary for rounding the mantissa. Refer to Table 3-21
for encoding information. .
1.2.3 Floating-Point Status Register (FPSR)
The FPSR (see Figure 1-2) contains a floating-point condition code (FPCC) byte, a floating-
point exception status (EXC) byte, a quotient byte, and a floating-point accrued exception
(AEXC) byte. The user can read or write to all the bits in the FPSR. Execution of most
floating-point instructions modifies this register. The reset function or a restore operation of
the null state clears the FPSR.
1.2.3.1 FLOATING-POINT CONDITION CODE BYTE. The FPCC byte, illustrated in
Figure 1-4, contains four condition code bits that set after completion of all arithmetic
instructions involving the floating-point data registers. The move floating-point data register
MOTOROLA
BSUN
15
SNAN OPERR
14
13
EXCEPTION ENABLE
M68000 FAMILY PROGRAMMER’S REFERENCE MANUAL
OVFL
12
Figure 1-3. Floating-Point Control Register
UNFL
11
10
DZ
INEX2 INEX1
9
8
7
PREC
6
5
RND
MODE CONTROL
4
3
ROUNDING MODE
ROUNDING PRECISION
INEXACT DECIMAL INPUT
INEXACT OPERATION
DIVIDE BY ZERO
UNDERFLOW
OVERFLOW
OPERAND ERROR
BRANCH/SET ON UNORDERED
SIGNALING NOT-A-NUMBER
2
0
1
Introduction
0
1-5