MC68EC000EI12 Freescale Semiconductor, MC68EC000EI12 Datasheet - Page 86

• Manufacturer Part Number: MC68EC000EI12
• Description: IC MPU 32BIT 12MHZ 68-PLCC
• Manufacturer: Freescale Semiconductor
• Series: 68K - M680X0r

Specifications of MC68EC000EI12

• Processor Type: M680x0 32-Bit
• Speed: 12MHz
• Voltage: 3.3V, 5V
• Mounting Type: Surface Mount
• Package / Case: 68-PLCC
• Core Size: 32 Bit
• Cpu Speed: 12MHz
• Digital Ic Case Style: PLCC
• No. Of Pins: 68
• Supply Voltage Range: 3V To 3.6V
• Operating Temperature Range: 0°C To +70°C
• Filter Terminals: SMD
• Rohs Compliant: Yes
• Clock Frequency: 12MHz
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Features: -

3.1.12 Memory Management Unit (MMU) Instructions
The PFLUSH instructions flush the address translation caches (ATCs) and can optionally
select only nonglobal entries for flushing. PTEST performs a search of the address
translation tables, stores the results in the MMU status register, and loads the entry into the
ATC. Table 3-13 summarizes these instructions.
3.1.13 Floating-Point Arithmetic Instructions
The following paragraphs describe the floating-point instructions, organized into two
categories of operation: dyadic (requiring two operands) and monadic (requiring one
operand).
The dyadic floating-point instructions provide several arithmetic functions that require two
input operands, such as add and subtract. For these operations, the first operand can be
located in memory, an integer data register, or a floating-point data register. The second
operand is always located in a floating-point data register. The results of the operation store
in the register specified as the second operand. All FPU operations support all data formats.
Results are rounded to either extended-, single-, or double-precision format. Table 3-14
gives the general format of dyadic instructions, and Table 3-15 lists the available operations.
MOTOROLA
Instruction Processor
PRESTORE
PFLUSHAN
PFLUSHA
PFLUSHN
PFLUSHS
PFLUSHR
PTRAPcc
PFLUSH
PMOVE
PLOAD
PSAVE
PTEST
PDBcc
PBcc
PScc
MC68851
MC68851
MC68030
MC68040
MC68851
MC68040
MC68040
MC68040
MC68851
MC68851
MC68030
MC68851
MC68030
MC68851
MC68851
MC68851
MC68851
MC68030
MC68040
MC68851
MC68851
M68000 FAMILY PROGRAMMER’S REFERENCE MANUAL
MRn,<ea>
<ea>,MRn
Operand
FC,<ea>
#<data>
Syntax
<label>
Dn,<la-
none
none
none
<ea>
<ea>
<ea>
<ea>
bel>
(An)
(An)
(An)
Table 3-13. MMU Operation Format
8,16,32,64 Move to/from MMU Registers
Operand
16,32
Size
none
none
none
none
none
none
none
none
none
none
none
none
8
Branch on PMMU Condition
Test, Decrement, and Branch
Invalidate All ATC Entries
Invalidate ATC Entries at Effective Address
Invalidate Nonglobal ATC Entries at Effective Address
Invalidate All Nonglobal ATC Entries
Invalidate All Shared/Global ATC Entries
Invalidate ATC and RPT Entries
Load an Entry into the ATC
PMMU Restore Function
PMMU Save Function
Set on PMMU Condition
Information About Logical Address
Trap on PMMU Condition
Operation
Instruction Set Summary
MMU Status Register
3-15