MC68EC000EI12 Freescale Semiconductor, MC68EC000EI12 Datasheet - Page 217

• Manufacturer Part Number: MC68EC000EI12
• Description: IC MPU 32BIT 12MHZ 68-PLCC
• Manufacturer: Freescale Semiconductor
• Series: 68K - M680X0r

Specifications of MC68EC000EI12

• Processor Type: M680x0 32-Bit
• Speed: 12MHz
• Voltage: 3.3V, 5V
• Mounting Type: Surface Mount
• Package / Case: 68-PLCC
• Core Size: 32 Bit
• Cpu Speed: 12MHz
• Digital Ic Case Style: PLCC
• No. Of Pins: 68
• Supply Voltage Range: 3V To 3.6V
• Operating Temperature Range: 0°C To +70°C
• Filter Terminals: SMD
• Rohs Compliant: Yes
• Clock Frequency: 12MHz
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Features: -

LSL, LSR
Operation:
Assembler
Syntax:
Attributes:
Description: Shifts the bits of the operand in the direction specified (L or R). The carry bit
MOTOROLA
receives the last bit shifted out of the operand. The shift count for the shifting of a
register is specified in two different ways:
The size of the operation for register destinations may be specified as byte, word, or
long. The contents of memory, < ea > , can be shifted one bit only, and the operand
size is restricted to a word.
The LSL instruction shifts the operand to the left the number of positions specified as
the shift count. Bits shifted out of the high-order bit go to both the carry and the extend
bits; zeros are shifted into the low-order bit.
The LSR instruction shifts the operand to the right the number of positions specified as
the shift count. Bits shifted out of the low-order bit go to both the carry and the extend
bits; zeros are shifted into the high-order bit.
1. Immediate—The shift count (1 – 8) is specified in the instruction.
2. Register—The shift count is the value in the data register specified in the in-
LSR:
LSL:
struction modulo 64.
M68000 FAMILY PROGRAMMER’S REFERENCE MANUAL
O
C
X
Destination Shifted By Count
LSd Dx,Dy
LSd # < data > ,Dy
LSd < ea >
where d is direction, L or R
Size = (Byte, Word, Long)
(M68000 Family)
Logical Shift
.
.
OPERAND
OPERAND
Destination
LSL, LSR
Integer Instructions
C
X
O
4-113