MC68EC000EI12 Freescale Semiconductor, MC68EC000EI12 Datasheet - Page 200

• Manufacturer Part Number: MC68EC000EI12
• Description: IC MPU 32BIT 12MHZ 68-PLCC
• Manufacturer: Freescale Semiconductor
• Series: 68K - M680X0r

Specifications of MC68EC000EI12

• Processor Type: M680x0 32-Bit
• Speed: 12MHz
• Voltage: 3.3V, 5V
• Mounting Type: Surface Mount
• Package / Case: 68-PLCC
• Core Size: 32 Bit
• Cpu Speed: 12MHz
• Digital Ic Case Style: PLCC
• No. Of Pins: 68
• Supply Voltage Range: 3V To 3.6V
• Operating Temperature Range: 0°C To +70°C
• Filter Terminals: SMD
• Rohs Compliant: Yes
• Clock Frequency: 12MHz
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Features: -

Integer Instructions
DIVU, DIVUL
Operation:
Assembler
Syntax:
Attributes:
Description:
Condition Codes:
4-96
operand and stores the unsigned result in the destination. The instruction uses one of
four forms. The word form of the instruction divides a long word by a word. The result
is a quotient in the lower word (least significant 16 bits) and a remainder in the upper
word (most significant 16 bits).
The first long form divides a long word by a long word. The result is a long quotient; the
remainder is discarded.
The second long form divides a quad word (in any two data registers) by a long word.
The result is a long-word quotient and a long-word remainder.
The third long form divides a long word by a long word. The result is a long-word quo-
tient and a long-word remainder.
Two special conditions may arise during the operation:
X — Not affected.
N — Set if the quotient is negative; cleared otherwise; undefined if overflow or divide
Z — Set if the quotient is zero; cleared otherwise; undefined if overflow or divide by
V — Set if division overflow occurs; cleared otherwise; undefined if divide by zero
C — Always cleared.
1. Division by zero causes a trap.
2. Overflow may be detected and set before the instruction completes. If the in-
—
X
struction detects an overflow, it sets the overflow condition code, and the oper-
ands are unaffected.
by zero occurs.
zero occurs.
occurs.
N
M68000 FAMILY PROGRAMMER’S REFERENCE MANUAL
Destination
DIVU.W < ea > ,Dn32/16
*DIVU.L < ea > ,Dq
*DIVU.L < ea > ,Dr:Dq
*DIVUL.L < ea > ,Dr:Dq
Size = (Word, Long)
Divides the unsigned destination operand by the unsigned source
*Applies to MC68020, MC68030, MC68040, CPU32 only.
Z
V
C
0
Source
Unsigned Divide
(M68000 Family)
Destination
32/32
64/32
32/32
16r – 16q
32q
32r – 32q
32r – 32q
DIVU, DIVUL
MOTOROLA