MC68EC000EI12 Freescale Semiconductor, MC68EC000EI12 Datasheet - Page 22

• Manufacturer Part Number: MC68EC000EI12
• Description: IC MPU 32BIT 12MHZ 68-PLCC
• Manufacturer: Freescale Semiconductor
• Series: 68K - M680X0r

Specifications of MC68EC000EI12

• Processor Type: M680x0 32-Bit
• Speed: 12MHz
• Voltage: 3.3V, 5V
• Mounting Type: Surface Mount
• Package / Case: 68-PLCC
• Core Size: 32 Bit
• Cpu Speed: 12MHz
• Digital Ic Case Style: PLCC
• No. Of Pins: 68
• Supply Voltage Range: 3V To 3.6V
• Operating Temperature Range: 0°C To +70°C
• Filter Terminals: SMD
• Rohs Compliant: Yes
• Clock Frequency: 12MHz
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Features: -

supported, where T0 is always zero, and only one system stack where the M-bit is always
zero. I2, I1, and I0 define the interrupt mask level.
1.3.3 Vector Base Register (VBR)
The VBR contains the base address of the exception vector table in memory. The
displacement of an exception vector adds to the value in this register, which accesses the
vector table.
1.3.4 Alternate Function Code Registers (SFC and DFC)
The alternate function code registers contain 3-bit function codes. Function codes can be
considered extensions of the 32-bit logical address that optionally provides as many as eight
4-Gbyte address spaces. The processor automatically generates function codes to select
address spaces for data and programs at the user and supervisor modes. Certain
instructions use SFC and DFC to specify the function codes for operations.
1.3.5 Acu Status Register (MC68EC030 only)
The access control unit status register (ACUSR) is a 16-bit register containing the status
information returned by execution of the PTEST instruction. The PTEST instruction
searches the access control (AC) registers to determine a match for a specified address. A
match in either or both of the AC registers sets bit 6 in the ACUSR. All other bits in the
ACUSR are undefined and must not be used.
MOTOROLA
MASTER/INTERRUPT STATE
SUPERVISOR/USER STATE
T1
0
1
0
1
T0
0
0
1
1
TRACE ON ANY INSTRUCTION
TRACE ON CHANGE OF FLOW
UNDEFINED
TRACE MODE
NO TRACE
15
T1
ENABLE
TRACE
M68000 FAMILY PROGRAMMER’S REFERENCE MANUAL
14
T0
13
S
SYSTEM BYTE
12
M
11
Figure 1-8. Status Register
0
10
I2
PRIORITY MASK
INTERRUPT
9
I1
I0
8
.
7
0
5 6
0
S
0
1
1
(CONDITION CODE REGISTER)
0
X
M
x
0
1
USER BYTE
4
N
ACTIVE STACK
ISP
MSP
USP
3
Z
2
V
1
C
0
CARRY
OVERFLOW
ZERO
NEGATIVE
EXTEND
Introduction
1-11