MC68EC000EI12 Freescale Semiconductor, MC68EC000EI12 Datasheet - Page 547

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MC68EC000EI12

Manufacturer Part Number
MC68EC000EI12
Description
IC MPU 32BIT 12MHZ 68-PLCC
Manufacturer
Freescale Semiconductor
Series
68K - M680X0r
Datasheets

Specifications of MC68EC000EI12

Processor Type
M680x0 32-Bit
Speed
12MHz
Voltage
3.3V, 5V
Mounting Type
Surface Mount
Package / Case
68-PLCC
Core Size
32 Bit
Cpu Speed
12MHz
Digital Ic Case Style
PLCC
No. Of Pins
68
Supply Voltage Range
3V To 3.6V
Operating Temperature Range
0°C To +70°C
Filter Terminals
SMD
Rohs Compliant
Yes
Clock Frequency
12MHz
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
Features
-

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Company
Part Number
Manufacturer
Quantity
Price
Part Number:
MC68EC000EI12
Manufacturer:
Freescale Semiconductor
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10 000
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Part Number:
MC68EC000EI12
Quantity:
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Part Number:
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TBLS
TBLSN
MOTOROLA
For register interpolate mode, the interpolation occurs using the Dym and Dyn registers
in place of the two table entries. For this mode, only the fractional portion, Dx 7 – 0, is
used in the interpolation, and the integer portion, Dx 15 – 8, is ignored. The register
interpolation mode may be used with several table lookup and interpolations to model
multidimensional functions.
Signed table entries range from – 2
range from 0 to 2
respectively.
Rounding of the result is optionally selected via the "R" instruction field. If R = 0
(TABLE), the fractional portion is rounded according to the round-to-nearest algorithm.
The following table summerizes the rounding procedure:
The adjusted difference is then added to the selected table entry. The rounded result
is returned in the destination data register, Dx. Only the portion of the register
corresponding to the selected size is affected.
WORD
LONG
BYTE
M68000 FAMILY PROGRAMMER’S REFERENCE MANUAL
31
Table Lookup and Interpolate (Signed)
UNAFFECTED
UNAFFECTED
n – 1
RESULT
where n is 8, 16, or 32 for byte, word, and long-word tables,
Adjusted Difference
> – 1/2 and < 1/2
24
Fraction
– 1/2
1/2
23
UNAFFECTED
UNAFFECTED
RESULT
n – 1
(CPU32)
to 2
16
n – 1
– 1; whereas, unsigned table entries
15
Adjustment
Rounding
UNAFFECTED
RESULT
RESULT
– 1
+ 0
+ 1
8
7
CPU32 Instructions
RESULT
RESULT
RESULT
TBLSN
TBLS
0
7-7

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