MC68EC000EI12 Freescale Semiconductor, MC68EC000EI12 Datasheet - Page 84

• Manufacturer Part Number: MC68EC000EI12
• Description: IC MPU 32BIT 12MHZ 68-PLCC
• Manufacturer: Freescale Semiconductor
• Series: 68K - M680X0r

Specifications of MC68EC000EI12

• Processor Type: M680x0 32-Bit
• Speed: 12MHz
• Voltage: 3.3V, 5V
• Mounting Type: Surface Mount
• Package / Case: 68-PLCC
• Core Size: 32 Bit
• Cpu Speed: 12MHz
• Digital Ic Case Style: PLCC
• No. Of Pins: 68
• Supply Voltage Range: 3V To 3.6V
• Operating Temperature Range: 0°C To +70°C
• Filter Terminals: SMD
• Rohs Compliant: Yes
• Clock Frequency: 12MHz
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Features: -

MOTOROLA
Letters cc in the TRAPcc and FTRAPcc specify testing for a condition.
MOVE from SR
MOVE from SR
Instruction
MOVE to SR
MOVE to SR
FRESTORE
ANDI to SR
EORI to SR
MOVE USP
ANDI to SR
EORI to SR
ORI to SR
ORI to SR
FTRAPcc
ILLEGAL
MOVEC
MOVES
TRAPcc
RESET
TRAPV
FSAVE
STOP
CHK2
TRAP
BKPT
CHK
RTE
#<data>,CCR
#<data>,CCR
#<data>,CCR
#<data>,SR
#<data>,SR
#<data>,SR
<ea>,CCR
CCR,<ea>
Operand
<ea>,SR
SR,<ea>
Rn,<ea>
<ea>,Rn
<ea>,Dn
<ea>,Rn
Syntax
#<data>
#<data>
#<data>
#<data>
#<data>
USP,An
An,USP
Rc,Rn
Rn,Rc
M68000 FAMILY PROGRAMMER’S REFERENCE MANUAL
<ea>
<ea>
none
none
none
none
none
none
Table 3-10. System Control Operation Format
Operand Size
8, 16, 32
8, 16, 32
16, 32
16, 32
16, 32
none
none
none
none
none
none
none
none
none
none
Condition Code Register
16
16
16
16
32
32
32
32
16
16
16
16
8
8
8
Trap Generating
Privileged
Immediate Data
Immediate Data
State Frame
Internal Floating-Point Registers
Source
SR
USP
An
Rc
Rn
Rn
Source Using SFC
Immediate Data V SR
Assert Reset Output
(SP)
Restore Stack According to Format
Immediate Data
Run Breakpoint Cycle
If Dn < 0 or Dn > (<ea>), Then CHK Exception
If Rn< Lower Bound or Rn > Upper Bound,
Then CHK Exception
SSP – 2
SSP – 2
If cc True, Then Trap Exception
If Floating-Point cc True, Then Trap Exception
If V, Then Take Overflow Trap Exception
Immediate Data
Immediate Data
Source
CCR
Immediate Data V CCR
SSP – 4
SSP – 2
Illegal Instruction Vector Address
SSP – 4
SR
USP
Rn
Rc
Destination Using DFC
Destination
(SSP); Vector Address
SR; SP + 2
An
Destination
SR
CCR
SSP; Vector Offset
SSP; Format and Vector Offset
SSP; PC
SSP; SR
SSP; PC
Internal Floating-Point Registers
SR
CCR
SR
CCR
SR; STOP
Rn
SP; (SP)
Operation
(SSP);
(SSP);
(SSP); SSP – 2
SR
SR
SR
CCR
CCR
CCR
Instruction Set Summary
PC
(SSP);
PC; SP + 4
State Frame
PC
SSP;
(SSP)
SP;
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