MC68EC000EI12 Freescale Semiconductor, MC68EC000EI12 Datasheet - Page 18

• Manufacturer Part Number: MC68EC000EI12
• Description: IC MPU 32BIT 12MHZ 68-PLCC
• Manufacturer: Freescale Semiconductor
• Series: 68K - M680X0r

Specifications of MC68EC000EI12

• Processor Type: M680x0 32-Bit
• Speed: 12MHz
• Voltage: 3.3V, 5V
• Mounting Type: Surface Mount
• Package / Case: 68-PLCC
• Core Size: 32 Bit
• Cpu Speed: 12MHz
• Digital Ic Case Style: PLCC
• No. Of Pins: 68
• Supply Voltage Range: 3V To 3.6V
• Operating Temperature Range: 0°C To +70°C
• Filter Terminals: SMD
• Rohs Compliant: Yes
• Clock Frequency: 12MHz
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Features: -

1.2.3.4 ACCRUED EXCEPTION BYTE. The AEXC byte contains five exception bits (see
Figure 1-7) required by the IEEE 754 standard for trap disabled operations. These
exceptions are logical combinations of the bits in the EXC byte. The AEXC byte contains a
history of all floating-point exceptions that have occurred since the user last cleared the
AEXC byte. In normal operations, only the user clears this byte by writing to the FPSR;
however, a reset or a restore operation of the null state can also clear the AEXC byte.
Many users elect to disable traps for all or part of the floating- point exception classes. The
AEXC byte makes it unnecessary to poll the EXC byte after each floating-point instruction.
At the end of most operations (FMOVEM and FMOVE excluded), the bits in the EXC byte
are logically combined to form an AEXC value that is logically ORed into the existing AEXC
byte. This operation creates "sticky" floating- point exception bits in the AEXC byte that the
user needs to poll only once—i.e., at the end of a series of floating-point operations.
Setting or clearing the AEXC bits neither causes nor prevents an exception. The following
equations show the comparative relationship between the EXC byte and AEXC byte.
Comparing the current value in the AEXC bit with a combination of bits in the EXC byte
derives a new value in the corresponding AEXC bit. These equations apply to setting the
AEXC bits at the end of each operation affecting the AEXC byte:
MOTOROLA
IOP
7
IOP
OVFL
UNFL
DZ
INEX
AEXC Bit
New
M68000 FAMILY PROGRAMMER’S REFERENCE MANUAL
OVFL
6
Figure 1-7. FPSR Accrued Exception Byte
UNFL
5
AEXC Bit
= OVFL
= UNFL
= INEX
= Old
= IOP
= DZ
DZ
4
INEX
3
V
V
V
V
V
V
.
2
EXC Bits
(SNAN V OPERR)
(OVFL)
(UNFL L INEX2)
(DZ)
(INEX1 V INEX2 V OVFL)
1
0
DIVIDE BY ZERO
UNDERFLOW
OVERFLOW
INVALID OPERATION
INEXACT
Introduction
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