MC68EC000EI12 Freescale Semiconductor, MC68EC000EI12 Datasheet - Page 85

• Manufacturer Part Number: MC68EC000EI12
• Description: IC MPU 32BIT 12MHZ 68-PLCC
• Manufacturer: Freescale Semiconductor
• Series: 68K - M680X0r

Specifications of MC68EC000EI12

• Processor Type: M680x0 32-Bit
• Speed: 12MHz
• Voltage: 3.3V, 5V
• Mounting Type: Surface Mount
• Package / Case: 68-PLCC
• Core Size: 32 Bit
• Cpu Speed: 12MHz
• Digital Ic Case Style: PLCC
• No. Of Pins: 68
• Supply Voltage Range: 3V To 3.6V
• Operating Temperature Range: 0°C To +70°C
• Filter Terminals: SMD
• Rohs Compliant: Yes
• Clock Frequency: 12MHz
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Features: -

Instruction Set Summary
3.1.10 Cache Control Instructions (MC68040)
The cache instructions provide maintenance functions for managing the instruction and data
caches. CINV invalidates cache entries in both caches, and CPUSH pushes dirty data from
the data cache to update memory. Both instructions can operate on either or both caches
and can select a single cache line, all lines in a page, or the entire cache. Table 3-11
summarizes these instructions.
3.1.11 Multiprocessor Instructions
The TAS, CAS, and CAS2 instructions coordinate the operations of processors in
multiprocessing systems. These instructions use read- modify-write bus cycles to ensure
uninterrupted updating of memory. Coprocessor instructions control the coprocessor
operations. Table 3- 12 summarizes these instructions.
3-14
cpRESTORE
Instruction
cpTRAPcc
cpSAVE
Instruction
cpDBcc
cpGEN
cpBcc
cpScc
CAS2
CPUSHP
CPUSHA
CAS
CPUSHL
TAS
CINVL
CINVP
CINVA
Dc1–Dc2, Du1–Du2,
Operand Syntax
Operand Syntax
M68000 FAMILY PROGRAMMER’S REFERENCE MANUAL
Table 3-11. Cache Control Operation Format
User Defined
caches, (An)
caches, (An)
Dc,Du,<ea>
caches,(An)
caches,(An)
<label>,Dn
(Rn)–(Rn)
#<data>
<label>
caches
caches
<ea>
<ea>
<ea>
<ea>
Table 3-12. Multiprocessor Operations
none
Operand Size
Read-Write-Modify
Operand Size
Coprocessor
User Defined
none
none
none
none
none
none
8, 16, 32
16, 32
16, 32
16, 32
none
none
none
16
8
8
Invalidate cache line
Invalidate cache page
Invalidate entire cache
Push selected dirty data cache lines, then
invalidate selected cache lines
Destination – Dc
Dual Operand CAS
Destination – 0; Set Condition Codes;
If cpcc True, Then PC + d
If cpcc False, Then Dn – 1
Operand
Restore Coprocessor State from <ea>
Save Coprocessor State at <ea>
If cpcc True, Then 1's
If cpcc True, Then TRAPcc Exception
If Z, Then Du
Else Destination
1
If Dn
Else 0's
Destination [7]
–1, Then PC + d
Destination
Coprocessor
Operation
Operation
Destination
CC
Dc
n
Destination;
n
PC
Dn
PC
MOTOROLA