MC68EC000EI12 Freescale Semiconductor, MC68EC000EI12 Datasheet - Page 457

• Manufacturer Part Number: MC68EC000EI12
• Description: IC MPU 32BIT 12MHZ 68-PLCC
• Manufacturer: Freescale Semiconductor
• Series: 68K - M680X0r

Specifications of MC68EC000EI12

• Processor Type: M680x0 32-Bit
• Speed: 12MHz
• Voltage: 3.3V, 5V
• Mounting Type: Surface Mount
• Package / Case: 68-PLCC
• Core Size: 32 Bit
• Cpu Speed: 12MHz
• Digital Ic Case Style: PLCC
• No. Of Pins: 68
• Supply Voltage Range: 3V To 3.6V
• Operating Temperature Range: 0°C To +70°C
• Filter Terminals: SMD
• Rohs Compliant: Yes
• Clock Frequency: 12MHz
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Features: -

CINV
Operation:
Assembler
Syntax:
Attributes:
Description: Invalidates selected cache lines. The data cache, instruction cache, both
Specific cache lines can be selected in three ways:
Condition Codes:
MOTOROLA
Not affected.
caches, or neither cache can be specified. Any dirty data in data cache lines that
invalidate are lost; the CPUSH instruction must be used when dirty data may be
contained in the data cache.
1. CINVL invalidates the cache line (if any) matching the physical address in the
2. CINVP invalidates the cache lines (if any) matching the physical memory page
3. CINVA invalidates all cache entries.
specified address register.
in the specified address register. For example, if 4K-byte page sizes are select-
ed and An contains $12345000, all cache lines matching page $12345000 in-
validate.
M68000 FAMILY PROGRAMMER’S REFERENCE MANUAL
If Supervisor State
ELSE TRAP
CINVL < caches > ,(An)
CINVP < caches > ,(An)
CINVA < caches >
Where < caches > specifies the instruction cache,
data cache, both caches, or neither cache.
Unsized
Then Invalidate Selected Cache Lines
Invalidate Cache Lines
(MC68040, MC68LC040)
Supervisor (Privileged) Instructions
CINV
6-3