MC68EC000EI12 Freescale Semiconductor, MC68EC000EI12 Datasheet - Page 414

• Manufacturer Part Number: MC68EC000EI12
• Description: IC MPU 32BIT 12MHZ 68-PLCC
• Manufacturer: Freescale Semiconductor
• Series: 68K - M680X0r

Specifications of MC68EC000EI12

• Processor Type: M680x0 32-Bit
• Speed: 12MHz
• Voltage: 3.3V, 5V
• Mounting Type: Surface Mount
• Package / Case: 68-PLCC
• Core Size: 32 Bit
• Cpu Speed: 12MHz
• Digital Ic Case Style: PLCC
• No. Of Pins: 68
• Supply Voltage Range: 3V To 3.6V
• Operating Temperature Range: 0°C To +70°C
• Filter Terminals: SMD
• Rohs Compliant: Yes
• Clock Frequency: 12MHz
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Features: -

Floating Point Instructions
FSGLDIV
Operation:
Assembler
Syntax:
Attributes:
Description: Converts the source operand to extended precision (if necessary) and divides
Operation Table:
5-112
that number into the number in the destination floating-point data register. Stores the
result in the destination floating-point data register, rounded to single precision (despite
the current rounding precision). This function is undefined for 0 0 and infinity infinity.
Both the source and destination operands are assumed to be representable in the sin-
gle-precision format. If either operand requires more than 24 bits of mantissa to be
accurately represented, the extraneous mantissa bits are trancated prior to the divi-
sion, hence the accuracy of the result is not guaranteed. Furthermore, the result expo-
nent may exceed the range of single precision, regardless of the rounding precision
selected in the floating-point control register mode control byte. Refer to 3.6.1 Under-
flow, Round, Overflow for more information.
The accuracy of the result is not affected by the number of mantissa bits required to
represent each input operand since the input operands just change to extended preci-
sion. The result mantissa is rounded to single precision, and the result exponent is
rounded to extended precision, despite the rounding precision selected in the floating-
point control register.
NOTES:
1. If the source operand is a NAN, refer to 1.6.5 Not-A-Numbers for more information.
2. Sets the DZ bit in the floating-point status register exception byte.
3. Sets the OPERR bit in the floating-point status register exception byte.
DESTINATION
In Range
Infinity
Zero
M68000 FAMILY PROGRAMMER’S REFERENCE MANUAL
FPn
FSGLDIV. < fmt > < ea > ,FPn
FSGLDIV.X
Format = (Byte, Word, Long, Single, Double, Extended, Packed)
+
+
–
–
+
–
+
+ 0.0
– 0.0
+ inf
– inf
Source
(Single Precision)
Single-Precision Divide
In Range
Divide
(MC6888X, MC68040)
FPn
FPm,FPn
+ 0.0
– 0.0
+ inf
– inf
– +
+ inf
– inf
+ inf
– inf
2
2
SOURCE
NAN
Zero
3
3,1
– inf
+ inf
+ inf
– inf
– +
2
2
+ 0.0
– 0.0
+ 0.0
– 0.0
FSGLDIV
Infinity
NAN
3
MOTOROLA
– 0.0
+ 0.0
– 0.0
+ 0.0
–