MC68EC000EI12 Freescale Semiconductor, MC68EC000EI12 Datasheet - Page 19

• Manufacturer Part Number: MC68EC000EI12
• Description: IC MPU 32BIT 12MHZ 68-PLCC
• Manufacturer: Freescale Semiconductor
• Series: 68K - M680X0r

Specifications of MC68EC000EI12

• Processor Type: M680x0 32-Bit
• Speed: 12MHz
• Voltage: 3.3V, 5V
• Mounting Type: Surface Mount
• Package / Case: 68-PLCC
• Core Size: 32 Bit
• Cpu Speed: 12MHz
• Digital Ic Case Style: PLCC
• No. Of Pins: 68
• Supply Voltage Range: 3V To 3.6V
• Operating Temperature Range: 0°C To +70°C
• Filter Terminals: SMD
• Rohs Compliant: Yes
• Clock Frequency: 12MHz
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Features: -

Introduction
1.2.4 Floating-Point Instruction Address Register (FPIAR)
The integer unit can be executing instructions while the FPU is simultaneously executing a
floating-point instruction. Additionally, the FPU can concurrently execute two floating-point
instructions. Because of this nonsequential instruction execution, the PC value stacked by
the FPU, in response to a floating-point exception trap, may not point to the offending
instruction.
For the subset of the FPU instructions that generate exception traps, the 32-bit FPIAR is
loaded with the logical address of the instruction before the processor executes it. The
floating-point exception handler can use this address to locate the floating-point instruction
that caused an exception. Since the FPU FMOVE to/from the FPCR, FPSR, or FPIAR and
FMOVEM instructions cannot generate floating- point exceptions, these instructions do not
modify the FPIAR. A reset or a null-restore operation clears the FPIAR.
1.3 SUPERVISOR PROGRAMMING MODEL
System programers use the supervisor programming model to implement sensitive
operating system functions—e.g., I/O control and memory management unit (MMU)
subsystems. The following paragraphs briefly describe the registers in the supervisor
programming model. They can only be accessed via privileged instructions. Table 1-1 lists
the supervisor registers and the processors not related to paged memory management. For
information concerning page memory management programming, refer to the device-
specific user’s manual. Table 1-2 lists the supervisor registers and the processors related to
paged memory management.
1-8
M68000 FAMILY PROGRAMMER’S REFERENCE MANUAL
MOTOROLA