MC68EC000EI12 Freescale Semiconductor, MC68EC000EI12 Datasheet - Page 92

• Manufacturer Part Number: MC68EC000EI12
• Description: IC MPU 32BIT 12MHZ 68-PLCC
• Manufacturer: Freescale Semiconductor
• Series: 68K - M680X0r

Specifications of MC68EC000EI12

• Processor Type: M680x0 32-Bit
• Speed: 12MHz
• Voltage: 3.3V, 5V
• Mounting Type: Surface Mount
• Package / Case: 68-PLCC
• Core Size: 32 Bit
• Cpu Speed: 12MHz
• Digital Ic Case Style: PLCC
• No. Of Pins: 68
• Supply Voltage Range: 3V To 3.6V
• Operating Temperature Range: 0°C To +70°C
• Filter Terminals: SMD
• Rohs Compliant: Yes
• Clock Frequency: 12MHz
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Features: -

Instruction Set Summary
extends the sign to the left, filling the register. The extract bit field unsigned (BFEXTU) also
loads a bit field, but zero fills the unused portion of the destination register.
The set bit field (BFSET) instruction sets all the bits of a field to ones. The clear bit field
(BFCLR) instruction clears a field. The change bit field (BFCHG) instruction complements
all the bits in a bit field. These three instructions all test the previous value of the bit field,
setting the condition codes accordingly. The test bit field (BFTST) instruction tests the value
in the field, setting the condition codes appropriately without altering the bit field. The find
first one in bit field (BFFFO) instruction scans a bit field from bit 0 to the right until it finds a
bit set to one and loads the bit offset of the first set bit into the specified data register. If no
bits in the field are set, the field offset and the field width is loaded into the register.
An important application of bit field instructions is the manipulation of the exponent field in a
floating-point number. In the IEEE standard format, the most significant bit is the sign bit of
the mantissa. The exponent value begins at the next most significant bit position; the
exponent field does not begin on a byte boundary. The extract bit field (BFEXTU) instruction
and the BFTST instruction are the most useful for this application, but other bit field
instructions can also be used.
Programming of input and output operations to peripherals requires testing, setting, and
inserting of bit fields in the control registers of the peripherals. This is another application for
bit field instructions. However, control register locations are not memory locations; therefore,
it is not always possible to insert or extract bit fields of a register without affecting other fields
within the register.
Another widely used application for bit field instructions is bit- mapped graphics. Because
byte boundaries are ignored in these areas of memory, the field definitions used with bit field
instructions are very helpful.
3.3.5 Pipeline Synchronization with the Nop Instruction
Although the no operation (NOP) instruction performs no visible operation, it serves an
important purpose. It forces synchronization of the integer unit pipeline by waiting for all
pending bus cycles to complete. All previous integer instructions and floating-point external
operand accesses complete execution before the NOP begins. The NOP instruction does
not synchronize the FPU pipeline—floating- point instructions with floating-point register
operand destinations can be executing when the NOP begins. NOP is considered a change
of flow instruction and traps for trace on change of flow. A single- cycle nonsynchronizing
operation can be affected with the TRAPF instruction.
3.4 FLOATING-POINT INSTRUCTION DETAILS
The following paragraphs describe the operation tables used in the instruction descriptions
and the conditional tests that can be used to change program flow based on floating-point
conditions. Details on NANs and floating-point condition codes are also discussed. The
IEEE 754 standard specifies that each data format must support add, subtract, multiply,
divide, remainder, square root, integer part, and compare. In addition to these arithmetic
MOTOROLA
M68000 FAMILY PROGRAMMER’S REFERENCE MANUAL
3-21