MC68EC000EI12 Freescale Semiconductor, MC68EC000EI12 Datasheet - Page 140

• Manufacturer Part Number: MC68EC000EI12
• Description: IC MPU 32BIT 12MHZ 68-PLCC
• Manufacturer: Freescale Semiconductor
• Series: 68K - M680X0r

Specifications of MC68EC000EI12

• Processor Type: M680x0 32-Bit
• Speed: 12MHz
• Voltage: 3.3V, 5V
• Mounting Type: Surface Mount
• Package / Case: 68-PLCC
• Core Size: 32 Bit
• Cpu Speed: 12MHz
• Digital Ic Case Style: PLCC
• No. Of Pins: 68
• Supply Voltage Range: 3V To 3.6V
• Operating Temperature Range: 0°C To +70°C
• Filter Terminals: SMD
• Rohs Compliant: Yes
• Clock Frequency: 12MHz
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Features: -

Integer Instructions
BFCLR
Instruction Fields:
4-36
Effective Address field—Specifies the base location for the bit field. Only data register
Do field—Determines how the field offset is specified.
Offset field—Specifies the field offset, depending on Do.
Dw field—Determines how the field width is specified.
Width field—Specifies the field width, depending on Dw.
0 — The offset field contains the bit field offset.
1 — Bits 8 – 6 of the extension word specify a data register that contains the offset;
If Do = 0, the offset field is an immediate operand; the operand value is in the range
If Do = 1, the offset field specifies a data register that contains the offset. The value
0 — The width field contains the bit field width.
1 — Bits 2 – 0 of the extension word specify a data register that contains the width;
If Dw = 0, the width field is an immediate operand; operand values in the range of 1
If Dw = 1, the width field specifies a data register that contains the width. The value
of 0 – 31.
is in the range of – 2
– 31 specify a field width of 1 – 31, and a value of zero specifies a width of 32.
is modulo 32; values of 1 – 31 specify field widths of 1 – 31, and a value of zero
specifies a width of 32.
direct or control alterable addressing modes can be used as listed in the following
table:
Addressing Mode Mode
bits 10 – 9 are zero.
bits 3 – 4 are zero.
([bd,An,Xn],od)
([bd,An],Xn,od)
(d
(bd,An,Xn)
(d
8
(An) +
– (An)
,An,Xn)
(An)
16
Dn
An
,An)
M68000 FAMILY PROGRAMMER’S REFERENCE MANUAL
(MC68020, MC68030, MC68040)
000
010
101
110
110
110
110
Test Bit Field and Clear
—
—
—
31
to 2
reg. number:Dn
reg. number:An
reg. number:An
reg. number:An
reg. number:An
reg. number:An
reg. number:An
31
Register
– 1.
—
—
—
Addressing Mode Mode
([bd,PC,Xn],od)
([bd,PC],Xn,od)
(bd,PC,Xn)
(d
(d
#<data>
(xxx).W
8
(xxx).L
,PC,Xn)
16
,PC)
111
111
—
—
—
—
—
—
BFCLR
Register
MOTOROLA
000
001
—
—
—
—
—
—