MC68EC000EI12 Freescale Semiconductor, MC68EC000EI12 Datasheet - Page 157

• Manufacturer Part Number: MC68EC000EI12
• Description: IC MPU 32BIT 12MHZ 68-PLCC
• Manufacturer: Freescale Semiconductor
• Series: 68K - M680X0r

Specifications of MC68EC000EI12

• Processor Type: M680x0 32-Bit
• Speed: 12MHz
• Voltage: 3.3V, 5V
• Mounting Type: Surface Mount
• Package / Case: 68-PLCC
• Core Size: 32 Bit
• Cpu Speed: 12MHz
• Digital Ic Case Style: PLCC
• No. Of Pins: 68
• Supply Voltage Range: 3V To 3.6V
• Operating Temperature Range: 0°C To +70°C
• Filter Terminals: SMD
• Rohs Compliant: Yes
• Clock Frequency: 12MHz
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Features: -

BKPT
Operation:
Assembler
Syntax:
Attributes:
Description: For the MC68010, a breakpoint acknowledge bus cycle is run with function
MOTOROLA
codes driven high and zeros on all address lines. Whether the breakpoint acknowledge
bus cycle is terminated with DTACK, BERR, or VPA, the processor always takes an
illegal instruction exception. During exception processing, a debug monitor can
distinguish different software breakpoints by decoding the field in the BKPT instruction.
For the MC68000 and MC68008, the breakpoint cycle is not run, but an illegal
instruction exception is taken.
For the MC68020, MC68030, and CPU32, a breakpoint acknowledge bus cycle is exe-
cuted with the immediate data (value 0 – 7) on bits 2 – 4 of the address bus and zeros
on bits 0 and 1 of the address bus. The breakpoint acknowledge bus cycle accesses
the CPU space, addressing type 0, and provides the breakpoint number specified by
the instruction on address lines A2 – A4. If the external hardware terminates the cycle
with DSACKx or STERM, the data on the bus (an instruction word) is inserted into the
instruction pipe and is executed after the breakpoint instruction. The breakpoint instruc-
tion requires a word to be transferred so, if the first bus cycle accesses an 8- bit port,
a second bus cycle is required. If the external logic terminates the breakpoint acknowl-
edge bus cycle with BERR (i.e., no instruction word available), the processor takes an
illegal instruction exception.
For the MC68040, this instruction executes a breakpoint acknowledge bus cycle.
Regardless of the cycle termination, the MC68040 takes an illegal instruction excep-
tion.
For more information on the breakpoint instruction refer to the appropriate user’s man-
ual on bus operation.
This instruction supports breakpoints for debug monitors and real- time hardware emu-
lators.
(MC68EC000, MC68010, MC68020, MC68030, MC68040, CPU32)
M68000 FAMILY PROGRAMMER’S REFERENCE MANUAL
Run Breakpoint Acknowledge Cycle; TRAP As Illegal Instruction
BKPT # < data >
Unsized
Breakpoint
Integer Instructions
BKPT
4-53