Z85C3008PSG Zilog, Z85C3008PSG Datasheet - Page 78

• Manufacturer Part Number: Z85C3008PSG
• Description: IC 8MHZ Z8500 CMOS SCC 40-DIP
• Manufacturer: Zilog
• Series: SCCr

Specifications of Z85C3008PSG

• Processor Type: Z80
• Features: Error Detection and Multiprotocol Support
• Speed: 8MHz
• Voltage: 5V
• Mounting Type: Through Hole
• Package / Case: 40-DIP (0.620", 15.75mm)
• Maximum Operating Temperature: + 70 C
• Minimum Operating Temperature: 0 C
• Mounting Style: Through Hole
• Cpu Speed: 8MHz
• Digital Ic Case Style: DIP
• No. Of Pins: 40
• Supply Voltage Range: 5V
• Operating Temperature Range: 0°C To +70°C
• Svhc: No SVHC (18-Jun-2010)
• Base Number: 85
• Rohs Compliant: Yes
• Clock Frequency: 8MHz
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Other names: 269-3930; Q2456016A; Z85C3008PSG

UM010901-0601
Incoming data is routed through one of several paths de-
pending on the mode and character length. In Asynchro-
nous mode, serial data enters the 3-bit delay if a character
length of seven or eight bits is selected. If a character
length of five or six bits is selected, data enters the receive
shift register directly.
In Synchronous modes, the data path is determined by the
phase of the receive process currently in operation. A syn-
chronous receive operation begins with a hunt phase in
which a bit pattern that matches the programmed sync
characters (6-,8-, or 16-bit) is searched.
The incoming data then passes through the Sync register
and is compared to a sync character stored in WR6 or
WR7 (depending on which mode it is in). The Monosync
mode matches the sync character programmed in WR7
and the character assembled in the Receive Sync register
to establish synchronization.
Synchronization is achieved differently in the Bisync
mode. Incoming data is shifted to the Receive Shift register
while the next eight bits of the message are assembled in
the Receive Sync register. If these two characters match
the programmed characters in WR6 and WR7, synchroni-
zation is established. Incoming data can then bypass the
Receive Sync register and enter the 3-bit delay directly.
The SDLC mode of operation uses the Receive Sync regis-
ter to monitor the receive data stream and to perform zero
deletion when necessary; i.e., when five continuous 1s are
received, the sixth bit is inspected and deleted from the data
stream if it is 0. The seventh bit is inspected only if the sixth
bit equals one. If the seventh bit is 0, a flag sequence has
4.2 ASYNCHRONOUS MODE
In asynchronous communications, data is transferred in
the format shown in Figure 4-3.
1
0
Idle State
of Line
Start
Figure 4-3. Asynchronous Message Format
Bit
LSB
Data Field
been received and the receiver is synchronized to that flag.
If the seventh bit is a 1, an abort or an EOP (End Of Poll) is
recognized, depending upon the selection of either the nor-
mal SDLC mode or SDLCLoop mode.
Note: The insertion and deletion of the zero in the SDLC
data stream is transparent to the user, as it is done after
the data is written to the Transmit FIFO and before data is
read from the Receive FIFO. This feature of the
SDLC/HDLC protocol is to prevent the inadvertent sending
of an ABORT sequence as part of the data stream. It is
also valuable to applications using encoded data to insure
a sufficient number of edges on the line to keep a DPLL
synchronized on a receive data stream.
The same path is taken by incoming data for both SDLC
and SDLC Loop modes. The reformatted data enters the
3-bit delay and is transferred to the Receive Shift register.
The SDLC receive operation begins in the hunt phase by
attempting to match the assembled character in the Re-
ceive Shift Register with the flag pattern in WR7. When the
flag character is recognized, subsequent data is routed
through the same path, regardless of character length.
Either the CRC-16 or CRC-SDLC (cyclic redundancy
check or CRC) polynomial can be used for both Monosync
and Bisync modes, but only the CRC-SDLC polynomial is
used for SDLC operation. The data path taken for each
mode is also different. Bisync protocol is a byte-oriented
operation that requires the CPU to decide whether or not a
data character is to be included in CRC calculation. An 8-
bit delay in all Synchronous modes except SDLC is al-
lowed for this process. In SDLC mode, all bytes are includ-
ed in the CRC calculation.
Parity
Bit
SCC™/ESCC™ User’s Manual
Bit(s)
1
Stop
1.5
Data Communication Modes
2
4-3
4