Z85C3008PSG Zilog, Z85C3008PSG Datasheet - Page 314

• Manufacturer Part Number: Z85C3008PSG
• Description: IC 8MHZ Z8500 CMOS SCC 40-DIP
• Manufacturer: Zilog
• Series: SCCr

Specifications of Z85C3008PSG

• Processor Type: Z80
• Features: Error Detection and Multiprotocol Support
• Speed: 8MHz
• Voltage: 5V
• Mounting Type: Through Hole
• Package / Case: 40-DIP (0.620", 15.75mm)
• Maximum Operating Temperature: + 70 C
• Minimum Operating Temperature: 0 C
• Mounting Style: Through Hole
• Cpu Speed: 8MHz
• Digital Ic Case Style: DIP
• No. Of Pins: 40
• Supply Voltage Range: 5V
• Operating Temperature Range: 0°C To +70°C
• Svhc: No SVHC (18-Jun-2010)
• Base Number: 85
• Rohs Compliant: Yes
• Clock Frequency: 8MHz
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Other names: 269-3930; Q2456016A; Z85C3008PSG

UM010901-0601
Q. Can the SCC detect multiple aborts?
A. The SCC searched for seven consecutive 1’s on the
Q. How do you send an end of poll (EOP) flag in SDLC
A. To send the EOP message, simply toggle the bit which
Q. When the SCC is programmed for 6 bit sync, how
A. Six bits are sent. The 12-bit sync character sends 12
Q. Do sync patterns (or flags) in data transmissions
A. All leading sync patterns (and all flags) are automati-
Q. How are the sync characters sent at the beginning
A. Load the transmit buffer with the first byte and the sync
receive data line for the abort detection. This condition
may be allowed to cause an external status interrupt.
After these seven 1’s are received, the receiver auto-
matically enters Hunt mode, where it looks for flags.
So, even if more than seven 1’s are received in case
of multiple aborts, only the first sequence of 1’s is sig-
nificant.
loop mode?
idles flags or ones to mark flags, then mark ones. This
produces a zero and more than seven 1’s; an EOP
condition.
are bits sent?
bits.
get stripped and still cause interrupts?
cally stripped if the Sync Character Load Inhibit fea-
ture is programmed. Any data stripped from the
transmission stream cannot cause a receive character
available interrupt but may cause other interrupts
(such as External/Status for Sync/Hunt and special re-
ceive condition for EOM).
of a Bisync frame?
characters are automatically sent out.
Q. How can you determine when the flag has been
A. There are several ways to determine if the flag has
Q. How do the DMA W/REQ lines operate?
A. DMA request lines follow the state of the transmit buff-
Q. How does the SCC handle messages less than
A. A 4-byte message consists of an address, control
completely sent?
been completely sent. This allows the transmitter to be
shut off, or in half duplex the line can be turned around.
This requires a little work by the user because the SCC
does not know when the last flag bit has been shifted
our. The following are some suggestions:
–
–
–
er.
four bytes in length?
word, no data, and 2 bytes of CRC. SDLC defines
messages of less than 4-bytes as an error. It is not de-
fined how the SCC will react, however, as tested by a
SCC user, 4-, 3-, and 2-byte messages cause an inter-
rupt on end of frame, but a 1 byte message does not
cause an interrupt.
Once the flag is loaded into the transmit shift
register, start an external clock. Use the baud rate
generator as the counter.
Tie the transmit line into DCD or an available input
pin, and watch for a zero, or end of flag. If you are
running half-duplex, use the local loopback mode
and watch for the flag to end.
Allow an abort, although this destroys the last
character. Be sure to send a dummy character -
then idle flags after the abort latch is set.
SCC™/ESCC™ User’s Manual
Zilog SCC
7-9