Z85C3008PSG Zilog, Z85C3008PSG Datasheet - Page 277

• Manufacturer Part Number: Z85C3008PSG
• Description: IC 8MHZ Z8500 CMOS SCC 40-DIP
• Manufacturer: Zilog
• Series: SCCr

Specifications of Z85C3008PSG

• Processor Type: Z80
• Features: Error Detection and Multiprotocol Support
• Speed: 8MHz
• Voltage: 5V
• Mounting Type: Through Hole
• Package / Case: 40-DIP (0.620", 15.75mm)
• Maximum Operating Temperature: + 70 C
• Minimum Operating Temperature: 0 C
• Mounting Style: Through Hole
• Cpu Speed: 8MHz
• Digital Ic Case Style: DIP
• No. Of Pins: 40
• Supply Voltage Range: 5V
• Operating Temperature Range: 0°C To +70°C
• Svhc: No SVHC (18-Jun-2010)
• Base Number: 85
• Rohs Compliant: Yes
• Clock Frequency: 8MHz
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Other names: 269-3930; Q2456016A; Z85C3008PSG

000002bb 10f0
000002bd 3e28
000002bf d3e8
000002c1 0e24
000002c3 cdWwww
000002c6741 l7:
000002c6 3aWwww
000002c9 cb4f
000002cb 28f9
000002cd cb8f
000002cf 32Wwww
000002d2 3e03
000002d4 d3e5
000002d6 3e05
000002d8 d3e8
000002da 3e60
000002dc d3e8
000002de 3e03
000002e0 d3e8
000002e2 3ecd
000002e4 d3e8
000002e6 0e26
000002e8 cdWwww
000002eb e1
000002ec c1
000002ed f1
000002ee c9
13-142
722
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djnz
ld
out
ld
call
ld
bit
jr
res
ld
ld
out
ld
out
ld
out
ld
out
ld
out
ld
call
pop
pop bc
pop
ret
txq2
a,028h
(scc_cont),a
c,24h
bittime
a,(timflg)
1,a
z,l7
1,a
(timflg),a
a,03h
(ctc1_cont),a
a,05h
(scc_cont),a
a,01100000b
(scc_cont),a
a,03h
(scc_cont),a
a,0cdh
(scc_cont),a
c,26h
bittime
hl
af
;loop until all
;bytes have been
;transmitted.
;reset tx int pending
;note:tx buffer
;empty happens as tx
;shifter is loaded.
;count= last byte+
;crc+flag+12bit times-btdelay
;btdelay=subr delay+ctc1int+polling=8bits
;8+16+8+12-8=36=24h
;bittime delay
;is stored in reg.c
;timer flag
;
;if bit1=1 then count finish
;
;reset timflg bit1
;update timflg
;
;
;disable int,software reset
;to kill counter
;****disable rs-422 driver after 12 to 18 1’s*****
;select WR5
;disable tx, set rts
;WR3
;8b/char,rx crc enabled,
;address search and rx enabled
;*************************************
;count for the interframe gap
;of 200 usec or 46 bit times.
;btdelay=subr delay+ctc1int+polling=8bits
;46 - btdelay=46-8=26h
;note that timflg will be polled in
;the main routine.
;
;
;bittime delay is stored in reg.c
;*************************************
;restore
;restore
;restore status and a reg
;
;
UM010901-0601