Z85C3008PSG Zilog, Z85C3008PSG Datasheet - Page 110

• Manufacturer Part Number: Z85C3008PSG
• Description: IC 8MHZ Z8500 CMOS SCC 40-DIP
• Manufacturer: Zilog
• Series: SCCr

Specifications of Z85C3008PSG

• Processor Type: Z80
• Features: Error Detection and Multiprotocol Support
• Speed: 8MHz
• Voltage: 5V
• Mounting Type: Through Hole
• Package / Case: 40-DIP (0.620", 15.75mm)
• Maximum Operating Temperature: + 70 C
• Minimum Operating Temperature: 0 C
• Mounting Style: Through Hole
• Cpu Speed: 8MHz
• Digital Ic Case Style: DIP
• No. Of Pins: 40
• Supply Voltage Range: 5V
• Operating Temperature Range: 0°C To +70°C
• Svhc: No SVHC (18-Jun-2010)
• Base Number: 85
• Rohs Compliant: Yes
• Clock Frequency: 8MHz
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Other names: 269-3930; Q2456016A; Z85C3008PSG

UM010901-0601
Write Register 0 (multiplexed bus mode)
D7 D6
0
0
1
1
* B Channel Only
Figure 5-1. Write Register 0 in the Z85X30
Figure 5-2. Write Register 0 in the Z80X30
Write Register 0 (non-multiplexed bus mode)
D7 D6 D5 D4
0
0
1
1
*
0
1
0
1
With Point High Command
0
1
0
1
D5 D4 D3 D2
0
0
0
0
1
1
1
1
Null Code
Reset Rx CRC Checker
Reset Tx CRC Generator
Reset Tx Underrun/EOM Latch
Reset Rx CRC Checker
Reset Tx CRC Generator
Reset Tx Underrun/EOM Latch
Null Code
0
0
0
0
1
1
1
1
0
0
1
1
0
0
1
1
0
0
1
0
0
1
1
1
0
1
0
1
0
1
0
1
D3 D2 D1 D0
1
0
1
0 Error Reset
0
1
0
1
Null Code
Null Code
Reset Ext/Status Interrupts
Send Abort
Enable Int on Next Rx Character
Reset Tx Int Pending
Error Reset
Reset Highest IUS
Point High
Reset Ext/Status Interrupts
Reset Tx Int Pending
Null Code
Enable Int on Next Rx Character
Reset Highest IUS
Send Abort (SDLC)
0
0
0
0
1
1
1
1
0
0
0
0
1
1
1
1
D1 D0
0
0
1
1
0
0
1
1
0
0
1
1
0
0
1
1
0
0
1
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
Null Code
Null Code
Select Shift Left Mode
Select Shift Right Mode
Register 0
Register 1
Register 2
Register 3
Register 4
Register 5
Register 6
Register 7
Register 8
Register 9
Register 10
Register 11
Register 12
Register 13
Register 14
Register 15
0
*
*
At the start of the CRC transmission, the Tx Under-
run/EOM latch is set. The Reset command can be issued
at any time during a message. If the transmitter is disabled,
this command does not reset the latch. However, if no Ex-
ternal Status interrupt is pending, or if a Reset External
Status interrupt command accompanies this command
while the transmitter is disabled, an External/Status inter-
rupt is generated with the Tx Underrun/EOM bit reset in
RR0.
Bits D5-D3: Command Codes for the SCC.
Null Command (000). The Null command has no effect on
the SCC.
Point High Command (001). This command effectively
adds eight to the Register Pointer (D2-D0) by allowing
WR8 through WR15 to be accessed. The Point High com-
mand and the Register Pointer bits are written simulta-
neously. This command is used in the Z85X30 version of
the SCC. Note that WR0 changes form depending upon
the SCC version. Register access for the Z80X30 version
of the SCC is accomplished through direct addressing.
Reset External/Status Interrupts Command (010). After
an External/Status interrupt (a change on a modem line or
a break condition, for example), the status bits in RR0 are
latched. This command re-enables the bits and allows in-
terrupts to occur again as a result of a status change.
Latching the status bits captures short pulses until the
CPU has time to read the change.
The SCC contains simple queueing logic associated with
most of the external status bits in RR0. If another Exter-
nal/Status condition changes while a previous condition is
still pending (Reset External/Status Interrupt has not yet
been issued) and this condition persists until after the com-
mand is issued, this second change causes another Exter-
nal/Status interrupt. However, if this second status change
does not persist (there are two transitions), another inter-
rupt is not generated. Exceptions to this rule are detailed
in the RR0 description.
Send Abort Command (011). This command is used in
SDLC mode to transmit a sequence of eight to thirteen 1s.
This command always empties the transmit buffer and
sets Tx Underrun/EOM bit in Read Register 0.
Enable Interrupt On Next Rx Character Command
(100). If the interrupt on First Received Character mode is
selected, this command is used to reactivate that mode af-
ter each message is received. The next character to enter
the Receive FIFO causes a Receive interrupt. Alternative-
ly, the first previously stored character in the FIFO causes
a Receive interrupt.
SCC™/ESCC™ User’s Manual
Register Descriptions
5-3
5