Z85C3008PSG Zilog, Z85C3008PSG Datasheet - Page 127

• Manufacturer Part Number: Z85C3008PSG
• Description: IC 8MHZ Z8500 CMOS SCC 40-DIP
• Manufacturer: Zilog
• Series: SCCr

Specifications of Z85C3008PSG

• Processor Type: Z80
• Features: Error Detection and Multiprotocol Support
• Speed: 8MHz
• Voltage: 5V
• Mounting Type: Through Hole
• Package / Case: 40-DIP (0.620", 15.75mm)
• Maximum Operating Temperature: + 70 C
• Minimum Operating Temperature: 0 C
• Mounting Style: Through Hole
• Cpu Speed: 8MHz
• Digital Ic Case Style: DIP
• No. Of Pins: 40
• Supply Voltage Range: 5V
• Operating Temperature Range: 0°C To +70°C
• Svhc: No SVHC (18-Jun-2010)
• Base Number: 85
• Rohs Compliant: Yes
• Clock Frequency: 8MHz
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Other names: 269-3930; Q2456016A; Z85C3008PSG

SCC™/ESCC™ User’s Manual
Register Descriptions
5.1 INTRODUCTION (Continued)
Set Source to BRG Command (100). Issuing this com-
mand forces the clock for the DPLL to come from the out-
put of the BRG.
Set Source to /RTxC Command (101). Issuing the com-
mand forces the clock for the DPLL to come from the
/RTxC pin or the crystal oscillator, depending on the state
of the XTAL/no XTAL bit in WR11. This mode is selected
by a channel or hardware reset.
Set FM Mode Command (110). This command forces the
DPLL to operate in the FM mode and is used to recover the
clock from FM or Manchester-Encoded data. (Manchester
is decoded by placing the receiver in NRZ mode while the
DPLL is in FM mode.)
Set NRZI Mode Command (111). Issuing this command
forces the DPLL to operate in the NRZI mode. This mode
is also selected by a hardware or channel reset.
Bit 4: Local Loopback select bit
Setting this bit to 1 selects the Local Loopback mode of op-
eration. In this mode, the internal transmitted data is routed
back to the receiver, and to the TxD pin. The /CTS and
/DCD inputs are ignored as enables in Local Loopback
mode, even if auto enable is selected. (If so programmed,
transitions on these inputs still cause interrupts.) This
mode works with any Transmit/Receive mode except Loop
mode. For meaningful results, the frequency of the trans-
mit and receive clocks must be the same. This bit is reset
by a channel or hardware reset.
Bit 3: Auto Echo select bit
Setting this bit to 1 selects the Auto Echo mode of opera-
tion. In this mode, the TxD pin is connected to RxD as in
Local Loopback mode, but the receiver still listens to the
RxD input. Transmitted data is never seen inside or out-
side the SCC in this mode, and /CTS is ignored as a trans-
mit enable. This bit is reset by a channel or hardware reset.
Bit 2: DTR/Request Function select bit
This bit selects the function of the /DTR//REQ pin following
the state of the DTR bit in WR5. If this is set to 0, the
/DTR//REQ pin follows the state of the DTR bit in WR5. If
this bit is set to 1, the /DTR//REQ pin goes Low whenever
the transmit buffer becomes empty and in any of the syn-
chronous modes when the CRC has been sent at the end
of a message. The request function on the /DTR//REQ pin
differs from the transmit request function available on the
/W//REQ pin. The /REQ does not go inactive until the inter-
nal operation satisfying the request is complete, which oc-
curs three to four PCLK cycles after the falling edge of /DS,
/RD or /WR. If the DMA used is edge-triggered, this differ-
ence is unimportant. The deassertion timing of the REQ
mode can be programmed to occur with the same timing
5-20
as the /W/REQ pin if WR7' D4=1. This bit is reset by a
channel or hardware reset.
Bit 1: Baud Rate Generator Source select bit
This bit selects the source of the clock for the baud rate
generator, If this bit is set to 0. The baud rate generator
clock comes from either the /RTxC pin or the XTAL oscil-
lator (depending on the state of the XTAL//no XTAL bit). If
this bit is set to 1, the clock for the baud rate generator is
the SCC’s PCLK input. Hardware reset sets this bit to 0,
select the /RTxC pin as the clock source for the BRG.
Bit 0: Baud Rate Generator Enable
This bit controls the operation of the BRG. The counter in
the BRG is enabled for counting when this bit is set to 1,
and counting is inhibited when this bit is set to 0. When this
bit is set to 1, change in the state of this bit is not reflected
by the output of the BRG for two counts of the counter.
This allows the command to be synchronized. However,
when set to 0, disabling is immediate. This bit is reset by a
hardware reset.
5.2.18 Write Register 15 (External/Status In-
terrupt Control)
WR15 is the External/Status Source Control register. If the
External/Status interrupts are enabled as a group via
WR1, bits in this register control which External/Status
conditions cause an interrupt. Only the External/Status
conditions that occur after the controlling bit is set to 1
cause an interrupt. This is true, even if an External/Status
condition is pending at the time the bit is set. Bit positions
for WR15 are shown in Figure 5-18.
On the CMOS version, bits D2 and D0 are reserved. On
the NMOS version, bit D2 is reserved. These reserved bits
should be written as 0s.
Write Register 15
D7
D6 D5
D4 D3
Figure 5-18. Write Register 15
D2 D1
D0
WR7' SDLC Feature Enable
(Reserved on NMOS/CMOS)
SDLC FIFO Enable (Reserved on NMOS)
Zero Count IE
DCD IE
Sync/Hunt IE
CTS IE
Tx Underrun/EOM IE
Break/Abort IE
UM010901-0601