Z85C3008PSG Zilog, Z85C3008PSG Datasheet - Page 122

• Manufacturer Part Number: Z85C3008PSG
• Description: IC 8MHZ Z8500 CMOS SCC 40-DIP
• Manufacturer: Zilog
• Series: SCCr

Specifications of Z85C3008PSG

• Processor Type: Z80
• Features: Error Detection and Multiprotocol Support
• Speed: 8MHz
• Voltage: 5V
• Mounting Type: Through Hole
• Package / Case: 40-DIP (0.620", 15.75mm)
• Maximum Operating Temperature: + 70 C
• Minimum Operating Temperature: 0 C
• Mounting Style: Through Hole
• Cpu Speed: 8MHz
• Digital Ic Case Style: DIP
• No. Of Pins: 40
• Supply Voltage Range: 5V
• Operating Temperature Range: 0°C To +70°C
• Svhc: No SVHC (18-Jun-2010)
• Base Number: 85
• Rohs Compliant: Yes
• Clock Frequency: 8MHz
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Other names: 269-3930; Q2456016A; Z85C3008PSG

UM010901-0601
Bit 0: Vector Includes Status control bit
The Vector Includes Status Bit controls whether or not the
SCC includes status information in the vector it places on
the bus in response to an interrupt acknowledge cycle. If
this bit is set, the vector returned is variable, with the vari-
able field depending on the highest priority IP that is set.
Table 5-5 shows the encoding of the status information.
This bit is ignored if the No Vector (NV) bit is set.
5.2.13 Write Register 10 (Miscellaneous
Transmitter/Receiver Control Bits)
WR10 contains miscellaneous control bits for both the
receiver and the transmitter. Bit positions for WR10 are
shown in Figure 5-12. On the ESCC and 85C30 with the
Extended Read option enabled, this register may be read
as RR11.
Write Register 10
D7 D6 D5 D4 D3
0
0
1
1
0 NRZ
1 NRZI
0
1
Figure 5-12. Write Register 10
FM1 (Transition = 1)
FM0 (Transition = 0)
D2 D1 D0
6-Bit//8-Bit Sync
Loop Mode
Abort//Flag On Underrun
Mark//Flag Idle
Go Active On Poll
CRC Preset I//O
Bit 7: CRC Presets I/O select bit
This bit specifies the initialized condition of the receive
CRC checker and the transmit CRC generator. If this bit is
set to 1, the CRC generator and checker are preset to 1. If
this bit is set to 0, the CRC generator and checker are pre-
set to 0. Either option can be selected with either CRC
polynomial. In SDLC mode, the transmitted CRC is invert-
ed before transmission, and the received CRC is checked
against the bit pattern 0001110100001111. This bit is re-
set by a channel or hardware reset. This bit is ignored in
Asynchronous mode.
Bits 6 and 5: Data Encoding select bits.
These bits control the coding method used for both the
transmitter and the receiver, as illustrated in Table 5-7. All
of the clocking options are available for all coding
methods. The DPLL in the SCC is useful for recovering
clocking information in NRZI and FM modes. Any coding
method can be used in X1 mode. A hardware reset forces
NRZ mode. Timing for the various modes is shown in
Figure 5-13.
Bit 6
0
0
1
1
Table 5-7. Data Encoding
Bit 5
0
1
0
1
SCC™/ESCC™ User’s Manual
Encoding
NRZ
NRZI
FM1 (transition = 1)
FM0 (transition = 0)
Register Descriptions
5-15
5