Z85C3008PSG Zilog, Z85C3008PSG Datasheet - Page 12

• Manufacturer Part Number: Z85C3008PSG
• Description: IC 8MHZ Z8500 CMOS SCC 40-DIP
• Manufacturer: Zilog
• Series: SCCr

Specifications of Z85C3008PSG

• Processor Type: Z80
• Features: Error Detection and Multiprotocol Support
• Speed: 8MHz
• Voltage: 5V
• Mounting Type: Through Hole
• Package / Case: 40-DIP (0.620", 15.75mm)
• Maximum Operating Temperature: + 70 C
• Minimum Operating Temperature: 0 C
• Mounting Style: Through Hole
• Cpu Speed: 8MHz
• Digital Ic Case Style: DIP
• No. Of Pins: 40
• Supply Voltage Range: 5V
• Operating Temperature Range: 0°C To +70°C
• Svhc: No SVHC (18-Jun-2010)
• Base Number: 85
• Rohs Compliant: Yes
• Clock Frequency: 8MHz
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Other names: 269-3930; Q2456016A; Z85C3008PSG

SCC™/ESCC™ User’s Manual
General Description
1.2 SCC’S CAPABILITIES
The NMOS version of the SCC is Zilog’s original device.
The design is based on the Z80 SIO architecture. If you are
familiar with the Z80 SIO, the SCC can be treated as an
SIO with support circuitry such as DPLL, BRG, etc. Its fea-
tures include:
1-2
Two independent full-duplex channels
Synchronous/Isosynchronous data rates:
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–
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Asynchronous Capabilities
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–
–
–
–
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Byte oriented synchronous capabilities:
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–
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SDLC/HDLC capabilities:
–
–
–
–
–
–
–
Up to 1/4 of the PCLK using external clock source.
Up to 5 Mbits/sec at 20 MHz PCLK (ESCC)
Up to 4 Mbits/sec at 16 MHz PCLK (CMOS)
Up to 2 MBits/sec at 8 MHz PCLK (NMOS)
Up to 1/8 of the PCLK (up to 1/16 on NMOS) using
FM encoding with DPLL
Up to 1/16 of the PCLK (up to 1/32 on NMOS)
using NRZI encoding with DPLL
5, 6, 7 or 8 bits/character (capable of handling 4
bits/character or less.)
1, 1.5, or 2 stop bits
Odd or even parity
Times 1, 16, 32 or 64 clock modes
Break generation and detection
Parity, overrun and framing error detection
Internal or external character synchronization
One or two sync characters (6 or 8 bits/sync
character) in separate registers
Automatic Cyclic Redundancy Check (CRC)
generation/detection
Abort sequence generation and checking
Automatic zero insertion and detection
Automatic flag insertion between messages
Address field recognition
I-field residue handling
CRC generation/detection
SDLC loop mode with EOP recognition/loop entry
and exit
The CMOS version of the SCC is 100% plug in compatible
to the NMOS versions of the device, while providing the
following additional features:
Receiver FIFO
Transmitter FIFO
NRZ, NRZI or FM encoding/decoding. Manchester code
decoding (encoding with external logic).
Baud Rate Generator in each channel
Digital Phase Locked Loop (DPLL) for clock recovery
Crystal oscillator
Status FIFO
Software interrupt acknowledge feature
Enhanced timing specifications
Faster system clock speed
Designed in Zilog’s Superintegration
When the DPLL clock source is external, it can be up to
2x the PCLK, where NMOS allows up to PCLK (32.3
MHz max with 16/20 MHz version).
NMOS/CMOS:
NMOS/CMOS:
ESCC:
ESCC:
8 bytes deep
3 bytes deep
4 bytes deep
1 byte deep
UM010901-0601
™
core format