Z85C3008PSG Zilog, Z85C3008PSG Datasheet - Page 312

• Manufacturer Part Number: Z85C3008PSG
• Description: IC 8MHZ Z8500 CMOS SCC 40-DIP
• Manufacturer: Zilog
• Series: SCCr

Specifications of Z85C3008PSG

• Processor Type: Z80
• Features: Error Detection and Multiprotocol Support
• Speed: 8MHz
• Voltage: 5V
• Mounting Type: Through Hole
• Package / Case: 40-DIP (0.620", 15.75mm)
• Maximum Operating Temperature: + 70 C
• Minimum Operating Temperature: 0 C
• Mounting Style: Through Hole
• Cpu Speed: 8MHz
• Digital Ic Case Style: DIP
• No. Of Pins: 40
• Supply Voltage Range: 5V
• Operating Temperature Range: 0°C To +70°C
• Svhc: No SVHC (18-Jun-2010)
• Base Number: 85
• Rohs Compliant: Yes
• Clock Frequency: 8MHz
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Other names: 269-3930; Q2456016A; Z85C3008PSG

UM010901-0601
ASYNCHRONOUS MODE
Q. Can the Sync Character Load Inhibit function strip
A. Yes. If not disabled it will strip any characters which
Q. What controls the DTR/WREQ pin?
A. The DTR pin follows the D7 bit in WR5 (inverse) as a
Q. How is the Asynchronous mode selected?
A. The Asyn mode is selected by programming the num-
Q. How are receiver breaks handled?
A. The SCC should monitor the break condition and wait
Q. Where can you get the DTR input if the DTR/REQ
A. The SYNC can be used as an input if operating in the
Q. When a special condition occurs due to a parity
A. No. In the case of Receive interrupt on Special Condi-
characters in Asynchronous mode if not disabled?
match the value in the sync character register. Always
disable this function in asynchronous mode (WR3, bit
D1).
Data Terminal Ready pin, or it is a DMA request line
(WREQ). The bit can be set or reset by writing to WR5.
ber of stop bits in write register 4.
for it to terminate. When the break condition stops, the
single NULL character in the receive buffer should be
read and discarded.
pin is being used for DMA?
Async mode. It will cause an interrupt on both transi-
tions.
error, will a receive interrupt for that byte still be
generated?
tion Only mode, the interrupt will not occur until after
the character with the special condition is read. In the
case of Receive Interrupt on All Characters or Special
Condition Only mode, the interrupt is generated on ev-
ery character whether or not it has a special condition.
Q. In the Auto Enable mode, what happens when
A. If the Auto Enable mode is selected, the CTS/ pin is an
Q. Can X1 clock mode really be used for the Async
A. X1 mode cannot be used unless the receive and trans-
Q. When does the FIFO buffer lock on an error
A. The receive data FIFO gets locked only in cases where
CTS/ goes inactive (high) in the middle of transfer-
ring a byte?
enable for the transmitter. So, when CTS/ is inactive,
transmit stops immediately.
operation?
mit clocks are synchronized. Using a synchronous mo-
dem is one way of satisfying this requirement.
condition?
the following receiver interrupt modes are selected:
–
–
In both of these modes, the Special Condition interrupt
occurs after the character with the special condition
has been read. The error status has to be valid when
read in the service routine. The Special Condition
locks the FIFO and guarantees that the DMA will not
transfer any characters until the Special Condition has
been serviced.
Receive Interrupt on Special Condition only
Receive Interrupt on First Character or Special
Condition
SCC™/ESCC™ User’s Manual
Zilog SCC
7-7